MPC8544E datasheet(14/117 Pages) FREESCALE

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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

Input Clocks

4.1

System Clock Timing

Table 5 provides the system clock (SYSCLK) AC timing specifications for the MPC8544E.

4.1.1

SYSCLK and Spread Spectrum Sources

Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference

emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise

magnitude in order to meet industry and government requirements. These clock sources intentionally add

long-term jitter in order to diffuse the EMI spectral content. The jitter specification given in Table 5

considers short-term (cycle-to-cycle) jitter only and the clock generator’s cycle-to-cycle output jitter

should meet the MPC8544E input cycle-to-cycle jitter requirement. Frequency modulation and spread are

separate concerns, and the MPC8544E is compatible with spread spectrum sources if the recommendations

listed in Table 6 are observed.

It is imperative to note that the processor’s minimum and maximum SYSCLK, core, and VCO frequencies

must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is

operated at its maximum rated e500 core frequency should avoid violating the stated limits by using

down-spreading only.

Table 5. SYSCLK AC Timing Specifications

At recommended operating conditions (see Table 2) with OVDD = 3.3 V ± 165 mV.

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

SYSCLK frequency

fSYSCLK

—

133

MHz

SYSCLK cycle time

tSYSCLK

7.5

—

30.3

—

SYSCLK rise and fall time

tKH, tKL

0.6

1.0

2.1

SYSCLK duty cycle

tKHK/tSYSCLK

—

SYSCLK jitter

—

±150

3, 4

Notes:

1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum

operating frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio

settings.

2. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.

3. This represents the total input jitter—short- and long-term.

4. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to allow

cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.

Table 6. Spread Spectrum Clock Source Recommendations

At recommended operating conditions. See Table 2.

Parameter

Min

Max

Unit

Notes

Frequency modulation

kHz

—

Frequency spread

1.0

Note:

1. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO frequencies, must meet the

minimum and maximum specifications given in Table 5.

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