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ADM1026JSTZ-R7 数据表(PDF) 47 Page - ON Semiconductor

部件名 ADM1026JSTZ-R7
功能描述  Complete Thermal System Management Controller
PDF  55 Pages
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制造商  ONSEMI [ON Semiconductor]
网页  http://www.onsemi.com
标志 ONSEMI - ON Semiconductor

ADM1026JSTZ-R7 数据表(HTML) 47 Page - ON Semiconductor

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Table 51. REGISTER 25H, STATUS REGISTER 6 (POWER-ON DEFAULT, 00H)
Bit
Name
R/W
(Note 1)
Description
0
GPIO8 Status = 0
R
R/W
When GPIO8 is configured as an input, this bit is set when GPIO8 is asserted.
(Asserted may be active high or active low depending on setting of Bit 1 in GPIO
Configuration Register 3.)
When GPIO8 is configured as an output, setting this bit asserts GPIO8. (Asserted
may be active high or active low depending on setting of Bit 1 in GPIO Configuration
Register 3.)
1
GPIO9 Status = 0
R
R/W
When GPIO9 is configured as an input, this bit is set when GPIO9 is asserted.
(Asserted may be active high or active low depending on setting of Bit 3 in GPIO
Configuration Register 3.)
When GPIO9 is configured as an output, setting this bit asserts GPIO9. (Asserted
may be active high or active low depending on setting of Bit 3 in GPIO Configuration
Register 3.)
2
GPIO10 Status = 0
R
R/W
When GPIO10 is configured as an input, this bit is set when GPIO10 is asserted.
(Asserted may be active high or active low depending on setting of Bit 5 in GPIO
Configuration Register 3.)
When GPIO10 is configured as an output, setting this bit asserts GPIO10. (Asserted
may be active high or active low depending on setting of Bit 5 in GPIO Configuration
Register 3.)
3
GPIO11 Status = 0
R
R/W
When GPIO11 is configured as an input, this bit is set when GPIO11 is asserted.
(Asserted may be active high or active low depending on setting of Bit 7 in GPIO
Configuration Register 3.)
When GPIO11 is configured as an output, setting this bit asserts GPIO11. (Asserted
may be active high or active low depending on setting of Bit 7 in GPIO Configuration
Register 3.)
4
GPIO12 Status = 0
R
R/W
When GPIO12 is configured as an input, this bit is set when GPIO12 is asserted.
(Asserted may be active high or active low depending on setting of Bit 1 in GPIO
Configuration Register 4.)
When GPIO12 is configured as an output, setting this bit asserts GPIO12. (Asserted
may be active high or active low depending on setting of Bit 1 in GPIO Configuration
Register 4.)
5
GPIO13 Status = 0
R
R/W
When GPIO13 is configured as an input , this bit is set when GPIO13 is asserted.
(Asserted may be active high or active low depending on setting of Bit 3 in GPIO
Configuration Register 4.)
When GPIO13 is configured as an output, setting this bit asserts GPIO13. (Asserted
may be active high or active low depending on setting of Bit 3 in GPIO Configuration
Register 4.)
6
GPIO14 Status = 0
R
R/W
When GPIO14 is configured as an input , this bit is set when GPIO14 is asserted.
(Asserted may be active high or active low depending on setting of Bit 5 in GPIO
Configuration Register 4.)
When GPIO14 is configured as an output, setting this bit asserts GPIO14. (Asserted
may be active high or active low depending on setting of Bit 5 in GPIO Configuration
Register 4.)
7
GPIO15 Status = 0
R
R/W
When GPIO15 is configured as an input, this bit is set when GPIO15 is asserted.
(Asserted may be active high or active low depending on setting of Bit 7 in GPIO
Configuration Register 4.)
When GPIO15 is configured as an output, setting this bit asserts GPIO15. (Asserted
may be active high or active low depending on setting of Bit 7 in GPIO Configuration
Register 4.)
1. GPIO status bits can be written only when a GPIO pin is configured as output. Read-only otherwise.
Table 52. REGISTER 26H, VBAT MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit
Name
R/W
Description
7–0
VBAT Value
R
This register contains the measured value of the VBAT analog input channel.
Table 53. REGISTER 27H, AIN8 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit
Name
R/W
Description
7–0
AIN8 Value
R
This register contains the measured value of the AIN8 analog input channel.



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