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ADM1026JSTZ-R7 数据表(PDF) 42 Page - ON Semiconductor

部件名 ADM1026JSTZ-R7
功能描述  Complete Thermal System Management Controller
PDF  55 Pages
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制造商  ONSEMI [ON Semiconductor]
网页  http://www.onsemi.com
标志 ONSEMI - ON Semiconductor

ADM1026JSTZ-R7 数据表(HTML) 42 Page - ON Semiconductor

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42
Table 39. REGISTER 19H, MASK REGISTER 2 (POWER-ON DEFAULT, 00H)
Bit
Name
R/W
Description
0
AIN0 Mask = 0
R/W
When this bit is set, interrupts generated on the AIN0 voltage channel are masked out.
1
AIN1 Mask = 0
R/W
When this bit is set, interrupts generated on the AIN1 voltage channel are masked out.
2
AIN2 Mask = 0
R/W
When this bit is set, interrupts generated on the AIN2 voltage channel are masked out.
3
AIN3 Mask = 0
R/W
When this bit is set, interrupts generated on the AIN3 voltage channel are masked out.
4
AIN4 Mask = 0
R/W
When this bit is set, interrupts generated on the AIN4 voltage channel are masked out.
5
AIN5 Mask = 0
R/W
When this bit is set, interrupts generated on the AIN5 voltage channel are masked out.
6
AIN6 Mask = 0
R/W
When this bit is set, interrupts generated on the AIN6 voltage channel are masked out.
7
AIN7 Mask = 0
R/W
When this bit is set, interrupts generated on the AIN7 voltage channel are masked out.
Table 40. REGISTER 1AH, MASK REGISTER 3 (POWER-ON DEFAULT, 00H)
Bit
Name
R/W
Description
0
FAN0 Mask = 0
R/W
When this bit is set, interrupts generated on the FAN0 tach channel are masked out.
1
FAN1 Mask = 0
R/W
When this bit is set, interrupts generated on the FAN1 tach channel are masked out.
2
FAN2 Mask = 0
R/W
When this bit is set, interrupts generated on the FAN2 tach channel are masked out.
3
FAN3 Mask = 0
R/W
When this bit is set, interrupts generated on the FAN3 tach channel are masked out.
4
FAN4 Mask = 0
R/W
When this bit is set, interrupts generated on the FAN4 tach channel are masked out.
5
FAN5 Mask = 0
R/W
When this bit is set, interrupts generated on the FAN5 tach channel are masked out.
6
FAN6 Mask = 0
R/W
When this bit is set, interrupts generated on the FAN6 tach channel are masked out.
7
FAN7 Mask = 0
R/W
When this bit is set, interrupts generated on the FAN7 tach channel are masked out.
Table 41. REGISTER 1BH, MASK REGISTER 4 (POWER-ON DEFAULT, 00H)
Bit
Name
R/W
Description
0
Int Temp Mask = 0
R/W
When this bit is set, interrupts generated on the internal temperature channel are
masked out.
1
VBAT Mask = 0
R/W
When this bit is set, interrupts generated on the VBAT voltage channel are masked out.
2
AIN8 Mask = 0
R/W
When this bit is set, interrupts generated on the AIN8 voltage channel are masked out.
3
THERM Mask = 0
R/W
When this bit is set, interrupts generated from THERM events are masked out.
4
AFC Mask = 0
R/W
When this bit is set, interrupts generated from automatic fan control events are
masked out.
5
Unused
R/W
Unused. Reads back 0.
6
CI Mask = 0
R/W
When this bit is set, interrupts generated by the chassis intrusion input are masked out.
7
GPIO16 Mask = 0
R/W
When this bit is set, interrupts generated on the GPIO16 channel are masked out.
Table 42. REGISTER 1CH, MASK REGISTER 5 (POWER-ON DEFAULT, 00H)
Bit
Name
R/W
Description
0
GPIO0 Mask = 0
R/W
When this bit is set, interrupts generated on the GPIO0 channel are masked out.
1
GPIO1 Mask = 0
R/W
When this bit is set, interrupts generated on the GPIO1 channel are masked out.
2
GPIO2 Mask = 0
R/W
When this bit is set, interrupts generated on the GPIO2 channel are masked out.
3
GPIO3 Mask = 0
R/W
When this bit is set, interrupts generated on the GPIO3 channel are masked out.
4
GPIO4 Mask = 0
R/W
When this bit is set, interrupts generated on the GPIO4 channel are masked out.
5
GPIO5 Mask = 0
R/W
When this bit is set, interrupts generated on the GPIO5 channel are masked out.
6
GPIO6 Mask = 0
R/W
When this bit is set, interrupts generated on the GPIO6 channel are masked out.
7
GPIO7 Mask = 0
R/W
When this bit is set, interrupts generated on the GPIO7 channel are masked out.



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