ADM1026JSTZ-R7 datasheet(41/55 Pages) ONSEMI

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ADM1026

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Table 33. REGISTER 13H, EEPROM REGISTER 3 (POWER-ON DEFAULT, 00H)

Bit

Name

R/W

Description

Read

R/W

Setting this bit puts the EEPROM into read mode.

Write

R/W

Setting this bit puts the EEPROM in write (program) mode.

Erase

R/W

Setting this bit puts the EEPROM into erase mode.

Write Protect

R/W

Once

Setting this bit protects the EEPROM against accidental writing or erasure. This bit

can write once and only be cleared by a power−on reset.

Test Mode Bit 0

R/W

Test mode bits. For factory use only

Test Mode Bit 1

R/W

Test mode bits. For factory use only.

Test Mode Bit 2

R/W

Test mode bits. For factory use only

Clock Extend

R/W

Setting this bit enables SMBus clock extension. The ADM1026 can pull SCL low to

extend the clock pulse if it cannot accept any more data. It is recommended to set

this bit to 1 to extend the clock pulse during repeated EEPROM write or block write

operations.

Table 34. REGISTER 14H, MANUFACTURER’S TEST REGISTER 1 (POWER-ON DEFAULT, 00H)

Bit

Name

R/W

Description

7–0

Manufacturer’s Test 1

R/W

This register is used by the manufacturer for test purposes. It should not be read

from or written to in normal operation.

Table 35. REGISTER 15H, MANUFACTURER’S TEST REGISTER 2 (POWER-ON DEFAULT, 00H)

Bit

Name

R/W

Description

7–0

Manufacturer’s Test 2

R/W

This register is used by the manufacturer for test purposes. It should not be read

from or written to in normal operation.

Table 36. REGISTER 16H, MANUFACTURER’S ID (POWER-ON DEFAULT, 041H)

Bit

Name

R/W

Description

7–0

Manufacturer ID Code

R/W

This register contains the manufacturer’s ID code.

Table 37. REGISTER 17H, REVISION REGISTER (POWER-ON DEFAULT, 4XH)

Bit

Name

R/W

Description

3–0

Minor Revision Code

This nibble contains the manufacturer’s code for minor revisions to the device.

Rev 1 = 0h, Rev 2 = 1h, and so on.

7–4

Major Revision Code

This nibble denotes the generation of the device. For the ADM1026, this nibble

reads 4h.

Table 38. REGISTER 18H, MASK REGISTER 1 (POWER-ON DEFAULT, 00H)

Bit

Name

R/W

Description

Ext1 Temp Mask = 0

R/W

When this bit is set, interrupts generated on the Ext1 temperature channel are

masked out.

Ext2 Temp

R/W

When this bit is set, interrupts generated on the Ext2/AIN9 channel are masked out.

3.3 V STBY Mask = 0

R/W

When this bit is set, interrupts generated on the 3.3 V STBY voltage channel are

masked out.

3.3 V MAIN Mask = 0

R/W

When this bit is set, interrupts generated on the 3.3 V MAIN voltage channel are

masked out.

+5.0 V Mask = 0

R/W

When this bit is set, interrupts generated on the +5.0 V voltage channel are masked

out.

VCCP Mask = 0

R/W

When this bit is set, interrupts generated on the VCCP voltage channel are masked out.

+12 V Mask = 0

R/W

When this bit is set, interrupts generated on the +12 V voltage channel are masked out.

−12 V Mask = 0

R/W

When this bit is set, interrupts generated on the −12 V voltage channel are masked out.

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