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ADM1026JSTZ-R7 数据表(PDF) 18 Page - ON Semiconductor |
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ADM1026JSTZ-R7 数据表(HTML) 18 Page - ON Semiconductor |
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18 / 55 page ![]() ADM1026 http://onsemi.com 18 This is a problem only if the ADC output must be full scale when the negative voltage is zero. Symmetrical bipolar input ranges can be accommodated easily by making VOS equal to the full-scale voltage of the analog input, and by adding a third resistor to set the positive full scale. Figure 29. Scaling and Offsetting AIN0 − AIN9 for Bipolar Inputs R1 R2 VIN AIN(0–9) R3 +VOS (eq. 5) R1 R2 + Vf s * VOS Note that R3 has no effect as the input voltage at the device pin is zero when VIN = negative full scale. (eq. 6) R1 R3 + Vf s * 3.0 3.0 for AIN0 through AIN5 R1 R3 + Vf s * 2.5 2.5 for AIN6 through AIN9 (eq. 7) Also, note that R2 has no effect as the input voltage at the device pin is equal to VOS when VIN = positive full scale. Battery Measurement Input (VBAT) The VBAT input allows the condition of a CMOS backup battery to be monitored. This is typically a lithium coin cell such as a CR2032. The VBAT input is accurate only for voltages greater than 1.5 V (see Figure 14). Typically, the battery in a system is required to keep some device powered on when the system is in a powered-off state. The VBAT measurement input is specially designed to minimize battery drain. To reduce current drain from the battery, the lower resistor of the VBAT attenuator is not connected, except whenever a VBAT measurement is being made. The total current drain on the VBAT pin is 80 nA typical (for a maximum VBAT voltage = 4.0 V), so a CR2032 CMOS battery functions in a system in excess of the expected 10 years. Note that when a VBAT measurement is not being made, the current drain is reduced to 6 nA typical. Under normal voltage measurement operating conditions, all measurements are made in a round-robin format, and each reading is actually the result of 16 digitally averaged measurements. However, averaging is not carried out on the VBAT measurement to reduce measurement time and therefore reduce the current drain from the battery. The VBAT current drain when a measurement is being made is calculated by: (eq. 8) I + VBAT 100 kW TPULSE TPERIOD For example, when VBAT = 3.0 V, (eq. 9) I + 3.0 V 100 kW 711 ms 273 ms + 78 nA where TPULSE = VBAT measurement time (711 ms typical), TPERIOD = time to measure all analog inputs (273 ms typical), and VBAT input battery protection. VBAT Input Battery Protection In addition to minimizing battery current drain, the VBAT measurement circuitry was specifically designed with battery protection in mind. Internal circuitry prevents the battery from being back-biased by the ADM1026 supply or through any other path under normal operating conditions. In the unlikely event of a catastrophic ADM1026 failure, the ADM1026 includes a second level of battery protection including a series 3 k W resistor to limit current to the battery, as recommended by UL. Thus, it is not necessary to add a series resistor between the battery and the VBAT input; the battery can be connected directly to the VBAT input to improve voltage measurement accuracy. Figure 30. Equivalent VBAT Input Protection Circuit ADC VBAT DIGITAL CONTROL 49.5k 82.7k 4.5pF 3k 3k Reference Output (VREF) The ADM1026 offers an on-chip reference voltage (Pin 24) that can be used to provide a 1.82 V or 2.5 V reference voltage output. This output is buffered and specified to sink or source a load current of 2 mA. The reference voltage outputs 1.82 V if Bit 2 of Configuration Register 3 (Address 07h) is 0; it outputs 2.5 V when this bit is set to 1. This voltage reference output can be used to provide a stable reference voltage to external circuitry such as LDOs. The load regulation of the VREF output is typically 0.15% for a sink current of 2 mA and 0.15% for 2 mA source current. There may be some ripple present on the VREF output that requires filtering (4m VMAX). Figure 31 shows the recommended circuitry for the VREF output for loads less than 2 mA. For loads in excess of 2 mA, external circuitry, such as that shown in Figure 32, can be used to buffer the VREF output. Figure 31. VREF Interface Circuit for VREF Loads < 2 mA 10k 0.1F VREF ADM1026 24 VREF |
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