ADM1026JSTZ-R7 datasheet(51/55 Pages) ONSEMI

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ADM1026

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Table 87. REGISTER 49H, EXT/AIN9 LOW LIMIT (POWER-ON DEFAULT 80H)

Bit

Name

R/W

Description

7–0

Ext2 Temp /AIN9 Low

Limit

R/W

This register contains the low limit of the Ext2 Temp/AIN9 channel depending on

which bit is configured.

Table 88. REGISTER 4AH, 3.3 V STBY LOW LIMIT (POWER-ON DEFAULT 00H)

Bit

Name

R/W

Description

7–0

3.3 V STBY Low Limit

R/W

This register contains the low limit of the 3.3 V STBY analog input channel.

Table 89. REGISTER 4BH, 3.3 V MAIN LOW LIMIT (POWER-ON DEFAULT 00H)

Bit

Name

R/W

Description

7–0

3.3 V MAIN Low Limit

R/W

This register contains the low limit of the 3.3 V MAIN analog input channel.

Table 90. REGISTER 4CH, +5.0 V LOW LIMIT (POWER-ON DEFAULT 00H)

Bit

Name

R/W

Description

7–0

+5.0 V Low Limit

R/W

This register contains the low limit of the +5.0 V analog input channel.

Table 91. REGISTER 4DH, VCCP LOW LIMIT (POWER-ON DEFAULT 00H)

Bit

Name

R/W

Description

7–0

VCCP Low Limit

R/W

This register contains the low limit of the VCCP analog input channel.

Table 92. REGISTER 4EH, +12 V LOW LIMIT (POWER-ON DEFAULT 00H)

Bit

Name

R/W

Description

7–0

+12 V Low Limit

R/W

This register contains the low limit of the +12 V analog input channel.

Table 93. REGISTER 4FH, −12 V LOW LIMIT (POWER-ON DEFAULT 00H)

Bit

Name

R/W

Description

7–0

−12 V Low Limit

R/W

This register contains the low limit of the -12 V analog input channel.

Table 94. REGISTER 50H, AIN0 HIGH LIMIT (POWER-ON DEFAULT FFH)

Bit

Name

R/W

Description

7–0

AIN0 High Limit

R/W

This register contains the high limit of the AIN0 analog input channel.

Table 95. REGISTER 51H, AIN1 HIGH LIMIT (POWER-ON DEFAULT FFH)

Bit

Name

R/W

Description

7–0

AIN1 High Limit

R/W

This register contains the high limit of the AIN1 analog input channel.

Table 96. REGISTER 52H, AIN2 HIGH LIMIT (POWER-ON DEFAULT FFH)

Bit

Name

R/W

Description

7–0

AIN2 High Limit

R/W

This register contains the high limit of the AIN2 analog input channel.

Table 97. REGISTER 53H, AIN3 HIGH LIMIT (POWER-ON DEFAULT FFH)

Bit

Name

R/W

Description

7–0

AIN3 High Limit

R/W

This register contains the high limit of the AIN3 analog input channel.

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