ADM1026JSTZ-R7 datasheet(7/55 Pages) ONSEMI

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ADM1026

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Table 4. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1, 2, and 3))

Parameter

Unit

Max

Typ

Min

Test Conditions/Comments

SERIAL BUS TIMING

Start Hold Time, tHD; STA

4.0

−

SCL Low Time, tLOW

4.7

−

SCL High Time, tHIGH

4.0

−

SCL, SDA Rise Time, tr

−

1000

SCL, SDA Fall Time, tf

−

300

Data Setup Time, tSU; DAT

250

−

Data Hold Time, tHD; DAT

300

−

1. All voltages are measured with respect to GND, unless otherwise specified.

2. Typicals are at TA = 25C and represent the most likely parametric norm. Shutdown current typ is measured with VCC = 3.3 V.

3. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge.

4. Total unadjusted error (TUE) includes offset, gain, and linearity errors of the ADC, multiplexer, and on-chip input attenuators. VBAT is accurate

only for VBAT voltages greater than 1.5 V (see Figure 14).

5. Total analog monitoring cycle time is nominally 273 ms, made up of 18 ms  11.38 ms measurements on analog input and internal

temperature channels, and 2 ms  34.13 ms measurements on external temperature channels.

6. The total fan count is based on two pulses per revolution of the fan tachometer output. The total fan monitoring time depends on the number

of fans connected and the fan speed. See the Fan Speed Measurement section for more details.

7. ADD is a three-state input that may be pulled high, low, or left open circuit.

8. Logic inputs accept input high voltages up to 5.0 V even when device is operating at supply voltages below 5.0 V.

9. Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117, and measured at −40C, +25C, and +85C. Typical endurance

at +25C is 700,000 cycles.

10.Retention lifetime equivalent at junction temperature (TJ ) = 55C as per JEDEC Std. 22 method A117. Retention lifetime based on activation

energy of 0.6 V derates with junction temperature as shown in Figure 15.

Figure 2. Serial Bus Timing Diagram

tSU; DAT

tHIGH

tHD; DAT

tLOW

tSU; STO

SCL

SDA

tBUF

tHD; STA

tSU; STA

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