AM186 datasheet(32/112 Pages) AMD

32 / 112 page

Am186TMER and Am188TMER Microcontrollers Data Sheet

DRAF

DRQ1–DRQ0

(DRQ1/PIO13, DRQ0/PIO12)

DMA Requests (input, synchronous,

level-sensitive)

These pins indicate to the microcontroller that an exter-

nal device is ready for DMA channel 1 or channel 0 to

perform a transfer. DRQ1–DRQ0 are level-triggered

and internally synchronized.

The DRQ signals are not latched and must remain ac-

tive until serviced.

DT/R/PIO4

Data Transmit or Receive (output, three-state,

synchronous)

This pin indicates which direction data should flow

through an external data-bus transceiver. When DT/R

is asserted High, the microcontroller transmits data.

When this pin is deasserted Low, the microcontroller

receives data. DT/R is three-stated during a bus hold or

reset condition.

GND

Ground

The ground pins connect the system ground to the mi-

crocontroller.

HLDA

Bus Hold Acknowledge (output, synchronous)

When an external bus master requests control of the

local bus (by asserting HOLD), the microcontroller

completes the bus cycle in progress and then relin-

quishes control of the bus to the external bus master by

asserting HLDA and floating DEN, RD, WR, S2–S0,

AD15–AD0, S6, A19–A0, BHE, WHB, WLB, and DT/R,

and then driving the chip selects UCS, LCS, MCS3–

MCS0, PCS6–PCS5, and PCS3–PCS0 High.

When the external bus master has finished using the

local bus, it indicates this to the microcontroller by

deasserting HOLD. The microcontroller responds by

deasserting HLDA.

If the microcontroller requires access to the bus (that is,

for refresh), it will deassert HLDA before the external

bus master deasserts HOLD. The external bus master

must be able to deassert HOLD and allow the micro-

controller access to the bus. See the timing diagrams

for bus hold on page 101. This pin is three-stated dur-

ing ONCE mode.

HOLD

Bus Hold Request (input, synchronous,

level-sensitive)

This pin indicates to the microcontroller that an external

bus master needs control of the local bus. For more in-

formation, see the HLDA pin description.

The Am186ER and Am188ER microcontrollers’ HOLD

latency time, the time between HOLD request and

HOLD acknowledge, is a function of the activity occur-

ring in the processor when the HOLD request is re-

ceived. A HOLD request is second only to DRAM or

PSRAM refresh requests in priority of activity requests

received by the processor. This implies that if a HOLD

request is received just as a DMA transfer begins, the

HOLD latency can be as great as four bus cycles. This

occurs if a DMA word transfer operation is taking place

(Am186ER microcontroller only) from an odd address

to an odd address. This is a total of 16 clock cycles or

more if wait states are required. In addition, if locked

transfers are performed, the HOLD latency time is in-

creased by the length of the locked transfer.

INT0

Maskable Interrupt Request 0 (input,

asynchronous)

This pin indicates to the microcontroller that an inter-

rupt request has occurred. If the INT0 pin is not

masked, the microcontroller transfers program execu-

tion to the location specified by the INT0 vector in the

microcontroller interrupt vector table.

Interrupt requests are synchronized internally and can

be edge-triggered or level-triggered. To guarantee in-

terrupt recognition, the requesting device must con-

tinue asserting INT0 until the request is acknowledged.

INT1/SELECT

Maskable Interrupt Request 1 (input,

asynchronous)

Slave Select (input, asynchronous)

INT1—This pin indicates to the microcontroller that an

interrupt request has occurred. If INT1 is not masked,

the microcontroller transfers program execution to the

location specified by the INT1 vector in the microcon-

troller interrupt vector table.

Interrupt requests are synchronized internally and can

be edge-triggered or level-triggered. To guarantee in-

terrupt recognition, the requesting device must con-

tinue asserting INT1 until the request is acknowledged.

SELECT—When the microcontroller interrupt control

unit is operating as a slave to an external master inter-

rupt controller, this pin indicates to the microcontroller

that an interrupt type appears on the address and data

bus. The INT0 pin must indicate to the microcontroller

that an interrupt has occurred before the SELECT pin

indicates to the microcontroller that the interrupt type

appears on the bus.

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