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AM186 数据表(PDF) 85 Page - Advanced Micro Devices |
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AM186 数据表(HTML) 85 Page - Advanced Micro Devices |
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85 / 112 page ![]() Am186TMER and Am188TMER Microcontrollers Data Sheet 85 DRAF T Switching Characteristics over Commercial and Industrial Operating Ranges PSRAM Refresh Cycle (40 MHz and 50 MHz) Notes: All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V. a Testing is performed with equal loading on referenced pins. Preliminary Parameter 40 MHz 50 MHz No. Symbol Description Min Max Min Max Unit General Timing Responses 9 tCHLH ALE Active Delay 12 10 ns 10 tLHLL ALE Width tCLCL–5=20 15 ns 11 tCHLL ALE Inactive Delay 12 10 ns Read/Write Cycle Timing Responses 25 tCLRL RD Active Delay 0 10 0 10 ns 26 tRLRH RD Pulse Width 2tCLCL–10=40 35 ns 27 tCLRH RD Inactive Delay 0 12 0 10 ns 28 tRHLH RD Inactive to ALE High(a) tCLCH–2 tCLCH–2 ns 80 tCLCLX LCS Inactive Delay 0 12 0 10 ns 81 tCLCSL LCS Active Delay 0 12 0 10 ns Refresh Timing Cycle Parameters 79 tCLRFD CLKOUTA Low to RFSH Valid 0 12 0 10 ns 82 tCLRF CLKOUTA High to RFSH Invalid 0 12 0 10 ns 85 tRFCY RFSH Cycle Time 6 x tCLCL 6 x tCLCL ns 86 tLCRF LCS Inactive to RFSH Active Delay 2tCLCL –1.25 2tCLCL –1.25 ns |
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