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AM186 数据表(PDF) 71 Page - Advanced Micro Devices |
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AM186 数据表(HTML) 71 Page - Advanced Micro Devices |
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71 / 112 page  Am186TMER and Am188TMER Microcontrollers Data Sheet 71 DRAF T Switching Characteristics over Commercial and Industrial Operating Ranges Read Cycle (40 MHz and 50 MHz) Notes: All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V. a Testing is performed with equal loading on referenced pins. b This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals. c If either specification 2 or specification 59 is met with respect to data hold time, the part will function correctly. Preliminary Parameter 40 MHz 50 MHz No. Symbol Description Min Max Min Max Unit General Timing Requirements 1 tDVCL Data in Setup 5 5 ns 2 tCLDX Data in Hold(c) 2 2 ns General Timing Responses 3 tCHSV Status Active Delay 0 12 0 10 ns 4 tCLSH Status Inactive Delay 0 12 0 10 ns 5 tCLAV AD Address Valid Delay 0 12 0 10 ns 7 tCLDV Data Valid Delay 0 12 0 10 ns 8 tCHDX Status Hold Time 0 0 ns 9 tCHLH ALE Active Delay 12 10 ns 10 tLHLL ALE Width tCLCL–5=20 15 ns 11 tCHLL ALE Inactive Delay 12 10 ns 12 tAVLL AD Address Valid to ALE Low(a) tCLCH tCLCH ns 13 tLLAX AD Address Hold from ALE Inactive(a) tCHCL tCHCL ns 14 tAVCH AD Address Valid to Clock High 0 0 ns 15 tCLAZ AD Address Float Delay tCLAX=0 12 0 10 ns 16 tCLCSV MCS/PCS Active Delay 0 12 0 10 ns 17 tCXCSX MCS/PCS Hold from Command Inactive(a) tCLCH tCLCH ns 18 tCHCSX MCS/PCS Inactive Delay 0 12 0 10 ns 19 tDXDL DEN Inactive to DT/R Low(a) 0 0 ns 20 tCVCTV Control Active Delay 1(b) 0 12 0 10 ns 21 tCVDEX DEN Inactive Delay 0 14 0 14 ns 22 tCHCTV Control Active Delay 2(b) 0 12 0 10 ns 23 tLHAV ALE High to Address Valid 7.5 5 ns Read Cycle Timing Responses 24 tAZRL AD Address Float to RD Active 0 0 ns 25 tCLRL RD Active Delay 0 10 0 10 ns 26 tRLRH RD Pulse Width 2tCLCL–10=40 35 ns 27 tCLRH RD Inactive Delay 0 12 0 10 ns 28 tRHLH RD Inactive to ALE High(a) tCLCH–2 tCLCH–2 ns 29 tRHAV RD Inactive to AD Address Active(a) tCLCL–5=20 15 ns 59 tRHDX RD High to Data Hold on AD Bus(c) 0 0 ns 66 tAVRL A Address Valid to RD Low 2 • tCLCL–10=40 2 • tCLCL–10=30 ns 67 tCHCSV CLKOUTA High to LCS/UCS Valid 0 12 0 10 ns 68 tCHAV CLKOUTA High to A Address Valid 0 10 0 10 ns |
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