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AM186 数据表(PDF) 99 Page - Advanced Micro Devices |
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AM186 数据表(HTML) 99 Page - Advanced Micro Devices |
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99 / 112 page  Am186TMER and Am188TMER Microcontrollers Data Sheet 99 DRAF T Switching Characteristics over Commercial and Industrial Operating Ranges Reset and Bus Hold (25 MHz and 33 MHz) Notes: All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V. a This timing must be met to guarantee recognition at the next clock. Switching Characteristics over Commercial and Industrial Operating Ranges Reset and Bus Hold (40 MHz and 50 MHz) Notes: All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V. a This timing must be met to guarantee recognition at the next clock. Preliminary Parameter 25 MHz 33 MHz No. Symbol Description Min Max Min Max Unit Reset and Bus Hold Timing Requirements 5 tCLAV AD Address Valid Delay 0 20 0 15 ns 15 tCLAZ AD Address Float Delay 0 20 0 15 ns 57 tRESIN RES Setup Time 10 8 ns 58 tHVCL HOLD Setup(a) 10 8 ns Reset and Bus Hold Timing Responses 62 tCLHAV HLDA Valid Delay 0 20 0 15 ns 63 tCHCZ Command Lines Float Delay 20 15 ns 64 tCHCV Command Lines Valid Delay (after Float) 20 15 ns Preliminary Parameter 40 MHz 50 MHz No. Symbol Description Min Max Min Max Unit Reset and Bus Hold Timing Requirements 5 tCLAV AD Address Valid Delay 0 12 0 10 ns 15 tCLAZ AD Address Float Delay 0 12 0 10 ns 57 tRESIN RES Setup Time 5 5 ns 58 tHVCL HOLD Setup(a) 5 5 ns Reset and Bus Hold Timing Responses 62 tCLHAV HLDA Valid Delay 0 12 0 10 ns 63 tCHCZ Command Lines Float Delay 12 10 ns 64 tCHCV Command Lines Valid Delay (after Float) 12 10 ns |
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