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AM186 数据表(PDF) 68 Page - Advanced Micro Devices |
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AM186 数据表(HTML) 68 Page - Advanced Micro Devices |
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68 / 112 page  68 Am186TMER and Am188TMER Microcontrollers Data Sheet DRAF T Alphabetical Key to Switching Parameter Symbols Notes: The following parameters are not defined or used at this time: 41, 56, 60, 73, 74, and 76. Parameter Symbol No. Description Parameter Symbol No. Description tARYCH 49 ARDY Resolution Transition Setup Time tCLDX 2 Data in Hold tARYCHL 51 ARDY Inactive Holding Time tCLEV 71 CLKOUTA Low to SDEN Valid tARYLCL 52 ARDY Setup Time tCLHAV 62 HLDA Valid Delay tAVBL 87 A Address Valid to WHB, WLB Low tCLRF 82 CLKOUTA High to RFSH Invalid tAVCH 14 AD Address Valid to Clock High tCLRH 27 RD Inactive Delay tAVLL 12 AD Address Valid to ALE Low tCLRL 25 RD Active Delay tAVRL 66 A Address Valid to RD Low tCLSH 4 Status Inactive Delay tAVWL 65 A Address Valid to WR Low tCLSL 72 CLKOUTA Low to SCLK Low tAZRL 24 AD Address Float to RD Active tCLSRY 48 SRDY Transition Hold Time tCH1CH2 45 CLKOUTA Rise Time tCLTMV 55 Timer Output Delay tCHAV 68 CLKOUTA High to A Address Valid tCOAOB 83 CLKOUTA to CLKOUTB Skew tCHCK 38 X1 High Time tCVCTV 20 Control Active Delay 1 tCHCL 44 CLKOUTA High Time tCVCTX 31 Control Inactive Delay tCHCSV 67 CLKOUTA High to LCS/UCS Valid tCVDEX 21 DEN Inactive Delay tCHCSX 18 MCS/PCS Inactive Delay tCXCSX 17 MCS/PCS Hold from Command Inactive tCHCTV 22 Control Active Delay 2 tDVCL 1 Data in Setup tCHCV 64 Command Lines Valid Delay (after Float) tDVSH 75 Data Valid to SCLK High tCHCZ 63 Command Lines Float Delay tDXDL 19 DEN Inactive to DT/R Low tCHDX 8 Status Hold Time tHVCL 58 HOLD Setup tCHLH 9 ALE Active Delay tINVCH 53 Peripheral Setup Time tCHLL 11 ALE Inactive Delay tINVCL 54 DRQ Setup Time tCHRFD 79 CLKOUTA High to RFSH Valid tLCRF 86 LCS Inactive to RFSH Active Delay tCHSV 3 Status Active Delay tLHAV 23 ALE High to Address Valid tCICOA 69 X1 to CLKOUTA Skew tLHLL 10 ALE Width tCICOB 70 X1 to CLKOUTB Skew tLLAX 13 AD Address Hold from ALE Inactive tCKHL 39 X1 Fall Time tLOCK 61 Maximum PLL Lock Time tCKIN 36 X1 Period tLRLL 84 LCS Precharge Pulse Width tCKLH 40 X1 Rise Time tRESIN 57 RES Setup Time tCL2CL1 46 CLKOUTA Fall Time tRFCY 85 RFSH Cycle Time tCLARX 50 ARDY Active Hold Time tRHAV 29 RD Inactive to AD Address Active tCLAV 5 AD Address Valid Delay tRHDX 59 RD High to Data Hold on AD Bus tCLAX 6 Address Hold tRHLH 28 RD Inactive to ALE High tCLAZ 15 AD Address Float Delay tRLRH 26 RD Pulse Width tCLCH 43 CLKOUTA Low Time tSHDX 77 SCLK High to SPI Data Hold tCLCK 37 X1 Low Time tSLDV 78 SCLK Low to SPI Data Valid tCLCL 42 CLKOUTA Period tSRYCL 47 SRDY Transition Setup Time tCLCLX 80 LCS Inactive Delay tWHDEX 35 WR Inactive to DEN Inactive tCLCSL 81 LCS Active Delay tWHDX 34 Data Hold after WR tCLCSV 16 MCS/PCS Active Delay tWHLH 33 WR Inactive to ALE High tCLDOX 30 Data Hold Time tWLWH 32 WR Pulse Width tCLDV 7 Data Valid Delay |
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