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AM186 数据表(PDF) 81 Page - Advanced Micro Devices

部件名 AM186
功能描述  High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM
PDF  112 Pages
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制造商  AMD [Advanced Micro Devices]
网页  http://www.amd.com
标志 AMD - Advanced Micro Devices

AM186 数据表(HTML) 81 Page - Advanced Micro Devices

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Am186TMER and Am188TMER Microcontrollers Data Sheet
81
DRAF
T
Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Write Cycle (25 MHz and 33 MHz)
Notes:
All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V.
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN, WR, WHB and WLB signals.
Preliminary
Parameter
25 MHz
33 MHz
No.
Symbol Description
Min
Max
Min
Max
Unit
General Timing Responses
5
tCLAV
AD Address Valid Delay
0
20
0
15
ns
7
tCLDV
Data Valid Delay
0
20
0
15
ns
8
tCHDX
Status Hold Time
0
0
ns
9
tCHLH
ALE Active Delay
20
15
ns
10
tLHLL
ALE Width
tCLCL–10=30
tCLCL–10=20
ns
11
tCHLL
ALE Inactive Delay
20
15
ns
23
tLHAV
ALE High to Address Valid
15
0
15
ns
20
tCVCTV Control Active Delay 1(b)
0
20
10
ns
80
tCLCLX LCS Inactive Delay
0
20
0
15
ns
81
tCLCSL LCS Active Delay
0
20
0
15
ns
84
tLRLL
LCS Precharge Pulse Width
tCLCL + tCLCH –3
tCLCL + tCLCH –3
Write Cycle Timing Responses
30
tCLDOX Data Hold Time
0
0
ns
31
tCVCTX Control Inactive Delay(b)
0
20
0
15
ns
32
tWLWH WR Pulse Width
2tCLCL–10=70
2tCLCL–10=50
ns
33
tWHLH
WR Inactive to ALE High(a)
tCLCH–2
tCLCH–2
ns
34
tWHDX
Data Hold after WR(a)
tCLCL–10=30
tCLCL–10=20
ns
65
tAVWL
A Address Valid to WR Low
tCLCL+tCHCL–3
tCLCL+tCHCL–3
ns
68
tCHAV
CLKOUTA High to A
Address Valid
0
20
0
15
ns
87
tAVBL
A Address Valid to WHB, WLB
Low
tCHCL–3
20
tCHCL–3
15
ns



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