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AM186 数据表(PDF) 79 Page - Advanced Micro Devices

部件名 AM186
功能描述  High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM
PDF  112 Pages
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制造商  AMD [Advanced Micro Devices]
网页  http://www.amd.com
标志 AMD - Advanced Micro Devices

AM186 数据表(HTML) 79 Page - Advanced Micro Devices

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Am186TMER and Am188TMER Microcontrollers Data Sheet
79
DRAF
T
Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Read Cycle (40 MHz and 50 MHz)
Notes:
All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V.
a
Testing is performed with equal loading on referenced pins.
b
If either specification 2 or specification 59 is met with respect to data hold time, the part will function correctly.
Preliminary
Parameter
40 MHz
50 MHz
No.
Symbol
Description
Min
Max
Min
Max
Unit
General Timing Requirements
1
tDVCL
Data in Setup
5
5
ns
2
tCLDX
Data in Hold(b)
2
2
ns
General Timing Responses
5
tCLAV
AD Address Valid Delay
0
12
0
10
ns
7
tCLDV
Data Valid Delay
0
12
0
10
ns
8
tCHDX
Status Hold Time
0
0
ns
9
tCHLH
ALE Active Delay
12
10
ns
10
tLHLL
ALE Width
tCLCL–5=20
15
ns
11
tCHLL
ALE Inactive Delay
12
10
ns
23
tLHAV
ALE High to Address Valid
7.5
5
ns
80
tCLCLX
LCS Inactive Delay
0
12
0
10
ns
81
tCLCSL
LCS Active Delay
0
12
0
10
ns
84
tLRLL
LCS Precharge Pulse Width
tCLCL + tCLCH –1.25
tCLCL + tCLCH –1
ns
Read Cycle Timing Responses
24
tAZRL
AD Address Float to RD Active
0
0
ns
25
tCLRL
RD Active Delay
0
10
0
10
ns
26
tRLRH
RD Pulse Width
2tCLCL–10=40
35
ns
27
tCLRH
RD Inactive Delay
0
12
0
10
ns
28
tRHLH
RD Inactive to ALE High(a)
tCLCH–1.25
tCLCH–1
ns
59
tRHDX
RD High to Data Hold on AD Bus(b)
0
0
ns
66
tAVRL
A Address Valid to RD Low
2tCLCL–10=40
2tCLCL–10=30
ns
68
tCHAV
CLKOUTA High to A Address Valid
0
10
0
10
ns



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