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Am186TMER and Am188TMER Microcontrollers Data Sheet

DRAF

FUNCTIONAL DESCRIPTION

The Am186ER and Am188ER microcontrollers are

based on the architecture of the original Am186 and

Am188 microcontrollers and they function in the en-

hanced mode of the Am186 and Am188 microcontrol-

lers. Enhanced mode includes system features such as

power-save control.

Each of the 8086, 8088, 80186, and 80188 microcon-

trollers contains the same basic set of registers, in-

structions, and addressing modes. The Am186ER and

Am188ER microcontrollers are backward compatible

with the 80C186/80C188 and Am186/Am188 micro-

controllers.

A full description of the Am186ER and Am188ER mi-

crocontrollers’ registers and instructions is included in

the

Am186ER and Am188ER Microcontrollers User’s

Manual, order #21684.

Memory Organization

Memory is organized in sets of segments. Each seg-

ment is a linear contiguous sequence of 64K (216) 8-bit

bytes. Memory is addressed using a two-component

address consisting of a 16-bit segment value and a 16-

bit offset. The 16-bit segment values are contained in

one of four internal segment registers (CS, DS, SS, or

ES). The physical address is calculated by shifting the

segment value left by 4 bits and adding the 16-bit offset

value to yield a 20-bit physical address (see Figure 3).

This allows for a 1-Mbyte physical address size.

All instructions that address operands in memory must

specify the segment value and the 16-bit offset value.

For speed and compact instruction encoding, the seg-

ment register used for physical address generation is

implied by the addressing mode used (see Table 7).

Figure 3.

Two-Component Address Example

I/O Space

The I/O space consists of 64K 8-bit or 32K 16-bit ports.

Separate instructions (IN, INS and OUT, OUTS)

address the I/O space with either an 8-bit port address

specified in the instruction, or a 16-bit port address in

the DX register. Eight-bit port addresses are zero-

extended such that A15–A8 are Low.

Table 7.

Segment Register Selection Rules

Segment

Base

Logical

Address

Shift

Left

4 Bits

Physical Address

To Memory

Offset

Memory Reference Needed

Segment Register Used Implicit Segment Selection Rule

Instructions

Code (CS)

Instructions (including immediate data)

Local Data

Data (DS)

All data references

Stack

Stack (SS)

All stack pushes and pops;

any memory references that use BP Register

External Data (Global)

Extra (ES)

All string instruction references that use the DI Register as an index

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