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AM186 数据表(PDF) 94 Page - Advanced Micro Devices |
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AM186 数据表(HTML) 94 Page - Advanced Micro Devices |
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94 / 112 page  94 Am186TMER and Am188TMER Microcontrollers Data Sheet DRAF T Switching Characteristics over Commercial and Industrial Operating Ranges Clock (40 MHz and 50 MHz) Notes: All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V. a The Times One mode should be used for operations from 16 MHz to 20 MHz. The Times Four mode should be used for operations above 20 MHz. Preliminary Parameter 40 MHz 50 MHz No. Symbol Description Min Max Min Max Unit CLKIN Requirements for Times Four Mode 36 tCKIN X1 Period(a) 100 125 80 125 ns 37 tCLCK X1 Low Time (1.5 V)(a) 45 35 ns 38 tCHCK X1 High Time (1.5 V)(a) 45 35 ns 39 tCKHL X1 Fall Time (3.5 to 1.0 V)(a) 5 5 ns 40 tCKLH X1 Rise Time (1.0 to 3.5 V)(a) 5 5 ns CLKIN Requirements for Times One Mode 36 tCKIN X1 Period(a) 25 60 Not Supported ns 37 tCLCK X1 Low Time (1.5 V)(a) 7.5 ns 38 tCHCK X1 High Time (1.5 V)(a) 7.5 ns 39 tCKHL X1 Fall Time (3.5 to 1.0 V)(a) 5 ns 40 tCKLH X1 Rise Time (1.0 to 3.5 V)(a) 5 ns CLKIN Requirements for Divide by Two Mode 36 tCKIN X1 Period(a) 12.5 33 Not Supported ns 37 tCLCK X1 Low Time (1.5 V)(a) 1.25 ns 38 tCHCK X1 High Time (1.5 V)(a) 1.25 ns 39 tCKHL X1 Fall Time (3.5 to 1.0 V)(a) 5 ns 40 tCKLH X1 Rise Time (1.0 to 3.5 V)(a) 5 ns CLKOUT Timing 42 tCLCL CLKOUTA Period 25 20 ns 43 tCLCH CLKOUTA Low Time (CL=50 pF) 0.5tCLCL–1.25=11.25 0.5tCLCL–1=9 ns 44 tCHCL CLKOUTA High Time (CL=50 pF) 0.5tCLCL–1.25=11.25 0.5tCLCL–1=9 ns 45 tCH1CH2 CLKOUTA Rise Time (1.0 to 3.5 V) 3 3 ns 46 tCL2CL1 CLKOUTA Fall Time (3.5 to 1.0 V) 3 3 ns 61 tLOCK Maximum PLL Lock Time 1 1 ms 69 tCICOA X1 to CLKOUTA Skew 20 15 ns 70 tCICOB X1 to CLKOUTB Skew 24 21 ns |
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