数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

AM186 数据表(PDF) 82 Page - Advanced Micro Devices

部件名 AM186
功能描述  High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM
PDF  112 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AMD [Advanced Micro Devices]
网页  http://www.amd.com
标志 AMD - Advanced Micro Devices

AM186 数据表(HTML) 82 Page - Advanced Micro Devices

Back Button AM186 Datasheet HTML 78Page - Advanced Micro Devices AM186 Datasheet HTML 79Page - Advanced Micro Devices AM186 Datasheet HTML 80Page - Advanced Micro Devices AM186 Datasheet HTML 81Page - Advanced Micro Devices AM186 Datasheet HTML 82Page - Advanced Micro Devices AM186 Datasheet HTML 83Page - Advanced Micro Devices AM186 Datasheet HTML 84Page - Advanced Micro Devices AM186 Datasheet HTML 85Page - Advanced Micro Devices AM186 Datasheet HTML 86Page - Advanced Micro Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 82 / 112 page
background image
82
Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAF
T
Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Write Cycle (40 MHz and 50 MHz)
Notes:
All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V.
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN, WR, WHB and WLB signals.
Preliminary
Parameter
40 MHz
50 MHz
No.
Symbol
Description
Min
Max
Min
Max
Unit
General Timing Responses
5
tCLAV
AD Address Valid Delay
0
12
0
10
ns
7
tCLDV
Data Valid Delay
0
12
0
10
ns
8
tCHDX
Status Hold Time
0
0
ns
9
tCHLH
ALE Active Delay
12
10
ns
10
tLHLL
ALE Width
tCLCL–5=20
15
ns
11
tCHLL
ALE Inactive Delay
12
10
ns
20
tCVCTV
Control Active Delay 1(b)
0
12
0
10
ns
23
tLHAV
ALE High to Address Valid
7.5
5
ns
80
tCLCLX
LCS Inactive Delay
0
12
0
10
ns
81
tCLCSL
LCS Active Delay
0
12
0
10
ns
84
tLRLL
LCS Precharge Pulse Width
tCLCL + tCLCH –1.25
tCLCL + tCLCH –1
Write Cycle Timing Responses
30
tCLDOX
Data Hold Time
0
0
ns
31
tCVCTX
Control Inactive Delay(b)
0
12
0
10
ns
32
tWLWH
WR Pulse Width
2tCLCL–10=40
35
ns
33
tWHLH
WR Inactive to ALE High(a)
tCLCH–2
tCLCH–2
ns
34
tWHDX
Data Hold after WR(a)
tCLCL–10=15
12
ns
65
tAVWL
A Address Valid to WR Low
tCLCL+tCHCL–1.25
tCLCL+tCHCL–1.25
ns
68
tCHAV
CLKOUTA High to A Address Valid
0
10
0
10
ns
87
tAVBL
A Address Valid to WHB, WLB Low
tCHCL–1.25
18
tCHCL–1.25
15
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com