AM186 datasheet(37/112 Pages) AMD

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Am186TMER and Am188TMER Microcontrollers Data Sheet

DRAF

S1/IMDIS

Bus Cycle Status (output, three-state,

synchronous)

Internal Memory Disable (input, internal pullup)

S1—This pin indicates to the system the type of bus

cycle in progress. S1 can be used as a data transmit or

receive indicator. S2–S0 are three-stated during bus

holds, hold acknowledges, and ONCE mode. During

reset, these pins are pullups. The S2–S0 pins are en-

coded as shown in Table 5.

IMDIS—If asserted during reset, this pin disables inter-

nal memory. Internal memory disable mode is provided

for emulation and debugging purposes.

S0/SREN

Bus Cycle Status (output, three-state,

synchronous)

Show Read Enable (input, internal pullup)

S0—This pin indicates to the system the type of bus

cycle in progress. S2–S0 are three-stated during bus

holds, hold acknowledges, and ONCE mode. During

reset, these pins are pullups. The S2–S0 pins are en-

coded as shown in Table 5.

SREN—If asserted during reset, this pin enables data

read from internal memory to be shown/driven on the

AD15–AD0 bus. Note that if a byte read is being shown,

the unused byte will also be driven on the AD15–AD0

bus.This mode is provided for emulation and debug-

ging purposes.

Table 5.

Bus Cycle Encoding

S6/CLKSEL1/PIO29

Bus Cycle Status Bit 6 (output, synchronous)

Clock Select 1 (input, internal pullup)

S6—During the second and remaining periods of a

cycle (t2, t3, and t4), this pin is asserted High to indicate

a DMA-initiated bus cycle. During a bus hold or reset

condition, S6 is three-stated.

CLKSEL1—The clocking mode of the Am186ER and

Am188ER microcontrollers is controlled by UZI/

CLKSEL2/PIO26 and S6/CLKSEL1/PIO29. Both

CLKSEL2 and CLKSEL1 are held High during power-

on reset because of an internal pullup resistor. This is

the default clocking mode—Times Four. If CLKSEL1 is

held Low during power-on reset, the chip enters the Di-

vide by Two clocking mode where the fundamental

clock is derived by dividing the external clock input by

2. If Divide by Two mode is selected, the PLL is dis-

abled. This pin is latched within three crystal clock cy-

cles after the rising edge of RES. Refer to Reset

Waveforms on page 100 and Signals Related to Reset

Waveforms on page 100 to determine signal hold

times. See Table 6 on page 39 for more information on

the clocking modes.

If S6 is used as PIO29 in input mode, the device driving

PIO29 must not drive the pin Low during power-on reset.

S6/CLKSEL1/PIO29 defaults to a PIO input with pullup,

so the pin does not need to be driven High externally.

SCLK/PIO20

Serial Clock (output, synchronous)

This pin supplies the synchronous serial interface (SSI)

clock to a slave device, allowing transmit and receive

operations to be synchronized between the microcon-

troller and the slave. SCLK is derived from the micro-

controller internal clock and then divided by 2, 4, 8, or

16 depending on register settings.

An access to any of the SSR or SSD registers acti-

vates SCLK for eight SCLK cycles (see Figure 14 and

Figure 15 on page 58). When SCLK is inactive, it is

held High by the microcontroller. SCLK is three-stated

during ONCE mode.

SDATA/PIO21

Serial Data (input/output, synchronous)

This pin transmits and receives synchronous serial in-

terface (SSI) data to and from a slave device. When

SDATA is inactive, a weak keeper holds the last value

of SDATA on the pin.

SDEN1/PIO23, SDEN0/PIO22

Serial Data Enables (output, synchronous)

These pins enable data transfers on port 1 and port 0

of the synchronous serial interface (SSI). The micro-

controller asserts either SDEN1 or SDEN0 at the be-

ginning of a transfer and deasserts it after the transfer

is complete. When SDEN1–SDEN0 are inactive, they

are held Low by the microcontroller. SDEN1–SDEN0

are three-stated during ONCE mode.

Bus Cycle

Interrupt acknowledge

Read data from I/O

Write data to I/O

Halt

Instruction fetch

Read data from memory

Write data to memory

None (passive)

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