AM186 datasheet(48/112 Pages) AMD

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Am186TMER and Am188TMER Microcontrollers Data Sheet

DRAF

Figure 10. Clock Organization

System Clocks

The base system clock of the original Am186/Am188

microcontrollers is renamed CLKOUTA and the addi-

tional output is called CLKOUTB. CLKOUTA and CLK-

OUTB operate at either the fundamental processor

frequency or the CPU clock (power-save) frequency.

Figure 10 shows the organization of the clocks.

The second clock output (CLKOUTB) allows one clock

to run at the fundamental frequency and the other clock

to run at the CPU (power-save) frequency. Individual

drive enable bits allow selective enabling of just one, or

both, of these clock outputs.

Power-Save Operation

T h e Power - Save mode of the Am186E R an d

Am188ER microcontrollers reduces power consump-

tion and heat dissipation, thereby extending battery life

in portable systems. In Power-Save mode, operation of

the CPU and internal peripherals continues at a slower

clock frequency. When a hardware interrupt occurs, the

microcontroller automatically returns to its normal op-

erating frequency. The microcontroller remains in

Power-Save mode for software interrupts and traps.

Note: Power-save operation requires that clock-

dependent peripherals be reprogrammed for clock

frequency changes. Software drivers must be aware of

clock frequency.

Initialization and Processor Reset

Processor initialization or startup is accomplished by

driving the RES input pin Low. RES must be held Low

for 1 ms during power-up to ensure proper device ini-

tialization. RES forces the Am186ER and Am188ER

microcontrollers to terminate all execution and local

bus activity. No instruction or bus activity occurs as long

as RES is active. After RES becomes inactive and an

internal processing interval elapses, the microcontrol-

ler begins execution with the instruction at physical lo-

cation FFFF0h. RES also sets some registers to

predefined values. Note that all clock selection (S6/

CLKSEL1 and UZI/CLKSEL2) must be stable four

clocks prior to the deassertion of RES. Activating the

PLL will require 1 ms to achieve a stable clock.

Reset Configuration Register

When the RES input is asserted Low, the contents of

the address/data bus (AD15–AD0) are written into the

Reset Configuration Register. The system can place

configuration information on the address/data bus

using weak external pullup or pulldown resistors, or

using an external driver that is enabled during reset.

The processor does not drive the address/data bus

during reset.

For example, the Reset Configuration Register could

be used to provide the software with the position of a

configuration switch in the system. Using weak external

pullup and pulldown resistors on the address and data

bus, the system would provide the microcontroller with

a value corresponding to the position of the jumper dur-

ing a reset.

The Reset Configuration Register can only be modified

during reset. This register is read-only during normal

operation.

Power-Save

Divisor1

(/1 to /128)

CBF1

Mux

CAF1

Mux

PSEN1

PLL

Mux

CLKOUTA

CLKOUTB

X1, X2

CPU Clock

Time

Delay

±2.5ns

÷2

Input Clock

CLKSEL2

CLKSEL1

CAD1

CBD1

Fundamental

Clock

1x or 4x

Mux

Notes:

1. Set via PDCON Register

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