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AM186 数据表(PDF) 96 Page - Advanced Micro Devices |
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AM186 数据表(HTML) 96 Page - Advanced Micro Devices |
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96 / 112 page  96 Am186TMER and Am188TMER Microcontrollers Data Sheet DRAF T Switching Characteristics over Commercial and Industrial Operating Ranges Ready and Peripheral Timing (25 MHz and 33 MHz) Notes: All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V. a This timing must be met to guarantee proper operation. b This timing must be met to guarantee recognition at the clock edge. Switching Characteristics over Commercial and Industrial Operating Ranges Ready and Peripheral Timing (40 MHz and 50 MHz) Notes: All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V. a This timing must be met to guarantee proper operation. b This timing must be met to guarantee recognition at the clock edge. Preliminary Parameter 25 MHz 33 MHz No. Symbol Description Min Max Min Max Unit Ready and Peripheral Timing Requirements 47 tSRYCL SRDY Transition Setup Time(a) 10 8 ns 48 tCLSRY SRDY Transition Hold Time(a) 3 3 ns 49 tARYCH ARDY Resolution Transition Setup Time(b) 10 8 ns 50 tCLARX ARDY Active Hold Time(a) 4 4 ns 51 tARYCHL ARDY Inactive Holding Time 4 4 ns 52 tARYLCL ARDY Setup Time(a) 15 10 ns 53 tINVCH Peripheral Setup Time(b) 10 8 ns 54 tINVCL DRQ Setup Time(b) 10 8 ns Peripheral Timing Responses 55 tCLTMV Timer Output Delay 20 15 ns Preliminary Parameter 40 MHz 50 MHz No. Symbol Description Min Max Min Max Unit Ready and Peripheral Timing Requirements 47 tSRYCL SRDY Transition Setup Time(a) 5 5 ns 48 tCLSRY SRDY Transition Hold Time(a) 2 2 ns 49 tARYCH ARDY Resolution Transition Setup Time(b) 5 5 ns 50 tCLARX ARDY Active Hold Time(a) 3 3 ns 51 tARYCHL ARDY Inactive Holding Time 5 5 ns 52 tARYLCL ARDY Setup Time(a) 5 5 ns 53 tINVCH Peripheral Setup Time(b) 5 5 ns 54 tINVCL DRQ Setup Time(b) 5 5 ns Peripheral Timing Responses 55 tCLTMV Timer Output Delay 12 10 ns |
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