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AM186 数据表(PDF) 74 Page - Advanced Micro Devices

部件名 AM186
功能描述  High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers with RAM
PDF  112 Pages
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制造商  AMD [Advanced Micro Devices]
网页  http://www.amd.com
标志 AMD - Advanced Micro Devices

AM186 数据表(HTML) 74 Page - Advanced Micro Devices

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74
Am186TMER and Am188TMER Microcontrollers Data Sheet
DRAF
T
Switching Characteristics over Commercial and Industrial Operating Ranges
Write Cycle (40 MHz and 50 MHz)
Notes:
All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V.
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals.
Preliminary
Parameter
40 MHz
50 MHz
No.
Symbol
Description
Min
Max
Min
Max
Unit
General Timing Responses
3
tCHSV
Status Active Delay
0
12
0
10
ns
4
tCLSH
Status Inactive Delay
0
12
0
10
ns
5
tCLAV
AD Address Valid Delay
0
12
0
10
ns
7
tCLDV
Data Valid Delay
0
12
0
10
ns
8
tCHDX
Status Hold Time
0
0
ns
9
tCHLH
ALE Active Delay
12
10
ns
10
tLHLL
ALE Width
tCLCL–5=20
15
ns
11
tCHLL
ALE Inactive Delay
12
10
ns
12
tAVLL
AD Address Valid to ALE Low(a)
tCLCH
tCLCH
ns
13
tLLAX
AD Address Hold from ALE Inactive(a)
tCHCL
tCHCL
ns
14
tAVCH
AD Address Valid to Clock High
0
0
ns
16
tCLCSV
MCS/PCS Active Delay
0
12
0
10
ns
17
tCXCSX
MCS/PCS Hold from Command
Inactive(a)
tCLCH
tCLCH
ns
18
tCHCSX
MCS/PCS Inactive Delay
0
12
0
10
ns
19
tDXDL
DEN Inactive to DT/R Low(a)
0
0
ns
20
tCVCTV
Control Active Delay 1(b)
0
12
0
10
ns
23
tLHAV
ALE High to Address Valid
7.5
5
ns
Write Cycle Timing Responses
30
tCLDOX
Data Hold Time
0
0
ns
31
tCVCTX
Control Inactive Delay(b)
0
12
0
10
ns
32
tWLWH
WR Pulse Width
2tCLCL–10=40
35
ns
33
tWHLH
WR Inactive to ALE High(a)
tCLCH–2
tCLCH–2
ns
34
tWHDX
Data Hold after WR(a)
tCLCL–10=15
12
ns
35
tWHDEX
WR Inactive to DEN Inactive(a)
tCLCH
tCLCH
ns
65
tAVWL
A Address Valid to WR Low
tCLCL+tCHCL–1.25
tCLCL+tCHCL–1.25
ns
67
tCHCSV
CLKOUTA High to LCS/UCS Valid
0
12
0
10
ns
68
tCHAV
CLKOUTA High to A Address Valid
0
10
0
10
ns
87
tAVBL
A Address Valid to WHB, WLB Low
tCHCL–1.25
12
tCHCL–1.25
10
ns



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