AM186 datasheet(52/112 Pages) AMD

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Am186TMER and Am188TMER Microcontrollers Data Sheet

DRAF

Peripheral Chip Selects

The Am186ER and Am188ER microcontrollers provide

six chip selects, PCS6–PCS5 and PCS3–PCS0, for

use within a user-locatable memory or I/O block. PCS4

is not available on the Am186ER and Am188ER micro-

controllers. The base address of the memory block can

be located anywhere within the 1-Mbyte memory ad-

dress space, exclusive of the areas associated with the

UCS, LCS, and MCS chip selects, or they can be con-

figured to access the 64-Kbyte I/O space.

The PCS pins are not active on reset. PCS6–PCS5 can

have from zero to three wait states. PCS3–PCS0 can

have four additional wait-state values—5, 7, 9, and 15.

Unlike the UCS and LCS chip selects, the PCS outputs

assert with the multiplexed AD address bus. Note also

that each peripheral chip select asser ts over a

256-byte address range, which is twice the address

range covered by peripheral chip selects in the 80C186

and 80C188 microcontrollers.

INTERNAL MEMORY

The Am186ER and Am188ER microcontrollers provide

32 Kbyte of on-chip RAM. The integration of memory

helps to reduce the overall cost, power, and size of sys-

tem designs. The internal memory also improves reli-

ability with fewer connections and eases inventory

management and system qualification because of the

integrated supply.

The internal RAM for the Am186ER microcontroller is a

16K x 16-bit-wide array (32 Kbyte) which provides the

same performance as 16-bit external zero-wait-state

RAM. For the Am188ER microcontroller, the internal

RAM is a 32K x 8-bit-wide array (32 Kbyte) that pro-

vides the same performance as 8-bit external zero

wait-state RAM.

Interaction with External RAM

The Am186ER and Am188ER microcontrollers include

an Internal Memory Chip Select (IMCS) Register to

control the mapping of the internal RAM. The internal

address space can be located at any 32-Kbyte bound-

ary within the 1-Mbyte memory address space, pro-

vided that it does not overlap any external chip selects.

If an overlap does occur, the external chip select must

be set to 0 wait states and to ignore external ready. If

the internal and external chip selects overlap, both will

be active, but the internal memory data will be used on

reads. Writes, with all the corresponding external con-

trol signals, will occur to both devices. Special system

consideration must be made for show read cycles,

since those cycles will drive data out on reads.

If internal and external chip selects overlap and the ex-

ternal chip selects are not set to 0 wait states and to ig-

nore external ready, the results are unpredictable.

Because of the many potential problems with overlap-

ping chip selects, this practice is not recommended.

The base address of the internal RAM is determined by

the value of bits BA19–BA15 in the IMCS Register. Be-

cause the interrupt vector table is located at 00000h, it

is not unusual to store the interrupt vector table in the

internal RAM for faster access, and thus program the

IMCS Register for a base address of 0. However, this

scenario may lead to a memory address overlap be-

tween the IMCS and low memory chip select (LMCS)

registers, as the base address of the LMCS Register is

always 0 if activated.

Emulator and Debug Modes

There are two debug modes associated with the inter-

nal memory. One mode allows users to disable the in-

ternal RAM, and the other mode makes it possible to

drive data on the external data bus during internal RAM

read cycles.

Normal operation of internal RAM has all control signals

for reads and writes and data for writes visible externally.

Accesses to internal memory can be detected externally

by comparing the address on A19–A0 with the address

space of the internal memory.

Internal Memory Disable

When this mode is activated, the internal RAM is dis-

abled and all accesses into the internal memory space

are made externally for debugging purposes. This

mode is activated by pulling the S1/IMDIS pin Low dur-

ing reset. To use this debug mode, internal memory

space must first be activated via the IMCS Register.

Show Read Enable

When this mode is activated, the data from the internal

RAM read cycles are driven on the AD15–AD0 bus.

Note that if a byte read is being shown, the unused byte

will also be driven on the AD15–AD0 bus. This mode

can be activated externally by pulling the S0/SREN pin

Low during reset or by setting the SR bit in the IMCS

SREN pin, the value of the SR bit is ignored. Many em-

ulators assert the SREN pin.

During an internal memory read with show read en-

abled, the address will be driven on the AD bus during

t1 and t2. The data being read will be driven on the AD

bus during t3 and t4 by the Am186ER or Am188ER mi-

crocontrollers. Special system care must be taken to

avoid bus contention, because normal reads have the

AD bus three-stated during t2, t3, and t4. It is best to en-

sure that no external device overlaps the internal mem-

ory space.

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