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AM186 数据表(PDF) 69 Page - Advanced Micro Devices |
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AM186 数据表(HTML) 69 Page - Advanced Micro Devices |
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69 / 112 page  Am186TMER and Am188TMER Microcontrollers Data Sheet 69 DRAF T Numerical Key to Switching Parameter Symbols Notes: The following parameters are not defined or used at this time: 41, 56, 60, 73, 74, and 76. Number Parameter Symbol Description Number Parameter Symbol Description 1 tDVCL Data in Setup 43 tCLCH CLKOUTA Low Time 2 tCLDX Data in Hold 44 tCHCL CLKOUTA High Time 3 tCHSV Status Active Delay 45 tCH1CH2 CLKOUTA Rise Time 4 tCLSH Status Inactive Delay 46 tCL2CL1 CLKOUTA Fall Time 5 tCLAV AD Address Valid Delay 47 tSRYCL SRDY Transition Setup Time 6 tCLAX Address Hold 48 tCLSRY SRDY Transition Hold Time 7 tCLDV Data Valid Delay 49 tARYCH ARDY Resolution Transition Setup Time 8 tCHDX Status Hold Time 50 tCLARX ARDY Active Hold Time 9 tCHLH ALE Active Delay 51 tARYCHL ARDY Inactive Holding Time 10 tLHLL ALE Width 52 tARYLCL ARDY Setup Time 11 tCHLL ALE Inactive Delay 53 tINVCH Peripheral Setup Time 12 tAVLL AD Address Valid to ALE Low 54 tINVCL DRQ Setup Time 13 tLLAX AD Address Hold from ALE Inactive 55 tCLTMV Timer Output Delay 14 tAVCH AD Address Valid to Clock High 57 tRESIN RES Setup Time 15 tCLAZ AD Address Float Delay 58 tHVCL HOLD Setup 16 tCLCSV MCS/PCS Active Delay 59 tRHDX RD High to Data Hold on AD Bus 17 tCXCSX MCS/PCS Hold from Command Inactive 61 tLOCK Maximum PLL Lock Time 18 tCHCSX MCS/PCS Inactive Delay 62 tCLHAV HLDA Valid Delay 19 tDXDL DEN Inactive to DT/R Low 63 tCHCZ Command Lines Float Delay 20 tCVCTV Control Active Delay 1 64 tCHCV Command Lines Valid Delay (after Float) 21 tCVDEX DEN Inactive Delay 65 tAVWL A Address Valid to WR Low 22 tCHCTV Control Active Delay 2 66 tAVRL A Address Valid to RD Low 23 tLHAV ALE High to Address Valid 67 tCHCSV CLKOUTA High to LCS/UCS Valid 24 tAZRL AD Address Float to RD Active 68 tCHAV CLKOUTA High to Address Valid 25 tCLRL RD Active Delay 69 tCICOA X1 to CLKOUTA Skew 26 tRLRH RD Pulse Width 70 tCICOB X1 to CLKOUTB Skew 27 tCLRH RD Inactive Delay 71 tCLEV CLKOUTA Low to SDEN Valid 28 tRHLH RD Inactive to ALE High 72 tCLSL CLKOUTA Low to SCLK Low 29 tRHAV RD Inactive to AD address Active 75 tDVSH Data Valid to SCLK High 30 tCLDOX Data Hold Time 77 tSHDX SCLK High to SPI Data Hold 31 tCVCTX Control Inactive Delay 78 tSLDV SCLK Low to SPI Data Valid 32 tWLWH WR Pulse Width 79 tCHRFD CLKOUTA High to RFSH Valid 33 tWHLH WR Inactive to ALE High 80 tCLCLX LCS Inactive Delay 34 tWHDX Data Hold after WR 81 tCLCSL LCS Active Delay 35 tWHDEX WR Inactive to DEN Inactive 82 tCLRF CLKOUTA High to RFSH Invalid 36 tCKIN X1 Period 83 tCOAOB CLKOUTA to CLKOUTB Skew 37 tCLCK X1 Low Time 84 tLRLL LCS Precharge Pulse Width 38 tCHCK X1 High Time 85 tRFCY RFSH Cycle Time 39 tCKHL X1 Fall Time 86 tLCRF LCS Inactive to RFSH Active Delay 40 tCKLH X1 Rise Time 87 tAVBL A Address Valid to WHB, WLB Low 42 tCLCL CLKOUTA Period |
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