AM186 datasheet(33/112 Pages) AMD

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Am186TMER and Am188TMER Microcontrollers Data Sheet

DRAF

INT2/INTA0/PIO31

Maskable Interrupt Request 2 (input,

asynchronous)

Interrupt Acknowledge 0 (output, synchronous)

INT2—This pin indicates to the microcontroller that an

interrupt request has occurred. If the INT2 pin is not

masked, the microcontroller transfers program execu-

tion to the location specified by the INT2 vector in the

microcontroller interrupt vector table.

Interrupt requests are synchronized internally and can

be edge-triggered or level-triggered. To guarantee in-

terrupt recognition, the requesting device must con-

tinue asserting INT2 until the request is acknowledged.

INT2 becomes INTA0 when INT0 is configured in cas-

cade mode.

INTA0—When the microcontroller interrupt control unit

is operating in cascade mode, this pin indicates to the

system that the microcontroller needs an interrupt type

to process the interrupt request on INT0. The periph-

eral issuing the interrupt request must provide the mi-

crocontroller with the corresponding interrupt type.

INT3/INTA1/IRQ

Maskable Interrupt Request 3

(input, asynchronous)

Interrupt Acknowledge 1 (output, synchronous)

Slave Interrupt Request (output, synchronous)

INT3—This pin indicates to the microcontroller that an

interrupt request has occurred. If the INT3 pin is not

masked, the microcontroller then transfers program ex-

ecution to the location specified by the INT3 vector in

the microcontroller interrupt vector table.

Interrupt requests are synchronized internally, and can

be edge-triggered or level-triggered. To guarantee in-

terrupt recognition, the requesting device must con-

tinue asserting INT3 until the request is acknowledged.

INT3 becomes INTA1 when INT1 is configured in cas-

cade mode.

INTA1—When the microcontroller interrupt control unit

is operating in cascade mode, this pin indicates to the

system that the microcontroller needs an interrupt type

to process the interrupt request on INT1. The periph-

eral issuing the interrupt request must provide the mi-

crocontroller with the corresponding interrupt type.

IRQ—When the microcontroller interrupt control unit is

operating as a slave to an external master interrupt

controller, this pin lets the microcontroller issue an in-

terrupt request to the external master interrupt control-

ler.

INT4/PIO30

Maskable Interrupt Request 4 (input,

asynchronous)

This pin indicates to the microcontroller that an inter-

rupt request has occurred. If the INT4 pin is not

masked, the microcontroller then transfers program ex-

ecution to the location specified by the INT4 vector in

the microcontroller interrupt vector table.

Interrupt requests are synchronized internally and can

be edge-triggered or level-triggered. To guarantee in-

terrupt recognition, the requesting device must con-

tinue asserting INT4 until the request is acknowledged.

LCS/ONCE0

Lower Memory Chip Select (output, synchronous,

internal pullup)

ONCE Mode Request 0 (input)

LCS—This pin indicates to the system that a memory

access is in progress to the lower memory block. The

size of the lower memory block is programmable up to

512 Kbyte. LCS is held High during a bus hold condi-

tion.

ONCE0—During reset, this pin and ONCE1 indicate to

the microcontroller the mode in which it should operate.

ONCE0 and ONCE1 are sampled on the rising edge of

RES. If both pins are asserted Low, the microcontroller

enters ONCE mode; otherwise, it operates normally.

In ONCE mode, all pins assume a high-impedance

state and remain in that state until a subsequent reset

occurs. To guarantee that the microcontroller does not

inadvertently enter ONCE mode, ONCE0 has a weak

internal pullup resistor that is active only during reset.

MCS3/RFSH/PIO25

Midrange Memory Chip Select 3

(output, synchronous, internal pullup)

Automatic Refresh (output, synchronous)

MCS3—This pin indicates to the system that a memory

access is in progress to the four th region of the

midrange memory block. The base address and size of

the midrange memory block are programmable. MCS3

is held High during a bus hold condition. In addition,

this pin has a weak internal pullup resistor that is active

during reset.

RFSH—This pin provides a signal timed for auto re-

fresh to PSRAM devices. It is only enabled to function

as a refresh pulse when the PSRAM mode bit is set in

the LMCS Register. An active Low pulse is generated

for 1.5 clock cycles with an adequate deassertion pe-

riod to ensure that overall auto refresh cycle time is

met.

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