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AM79C978VC/W 数据表(PDF) 109 Page - Advanced Micro Devices |
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AM79C978VC/W 数据表(HTML) 109 Page - Advanced Micro Devices |
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109 / 261 page  Am79C978 109 the host. It is cleared by H_RESET and is not affected by S_RESET or by setting the STOP bit. PCI Interrupt Pin Register Offset 3Dh This PCI Interrupt Pin register is an 8-bit register that indicates the interrupt pin that the Am79C978 controller is using. The value for the Am79C978 Interrupt Pin reg- ister is 01h, which corresponds to INTA. The PCI Interrupt Pin register is located at offset 3Dh in the PCI Configuration Space. It is read only. PCI MIN_GNT Register Offset 3Eh The PCI MIN_GNT register is an 8-bit register that specifies the minimum length of a burst period that the Am79C978 device needs to keep up with the network activity. The length of the burst period is calculated as- suming a clock rate of 33 MHz. The register value specifies the time in units of 1/4 µs. The PCI MIN_GNT register is an alias of BCR22, bits 7-0. It is recom- mended that BCR22 be programmed to a value of 1818h. The host should use the value in this register to deter- mine the setting of the PCI Latency Timer register. The PCI MIN_GNT register is located at offset 3Eh in the PCI Configuration Space. It is read only. PCI MAX_LAT Register Offset 3Fh The PCI MAX_LAT register is an 8-bit register that spec- ifies the maximum arbitration latency the Am79C978 controller can sustain without causing problems to the network activity. The register value specifies the time in units of 1/4 µs. The MAX_LAT register is an alias of BCR22, bits 15-8. It is recommended that BCR22 be programmed to a value of 1818h. The host should use the value in this register to deter- mine the setting of the PCI Latency Timer register. The PCI MAX_LAT register is located at offset 3Fh in the PCI Configuration Space. It is read only. PCI Capability Identifier Register Offset 40h Bit Name Description 7-0 CAP_ID This register, when set to 1, iden- tifies the linked list item as being the PCI Power Management reg- isters. This register has a default value of 1h. The PCI Capabilities Identifier register is located at offset 40h in the PCI Configuration Space. It is read only. PCI Next Item Pointer Register Offset 41h Bit Name Description 7-0 NXT_ITM_PTR The Next Item Pointer Register points to the starting address of the next capability. The pointer at this offset is a null pointer, indi- cating that this is the last capabil- ity in the linked list of the capabilities. This register has a default value of 0h. The PCI Next Pointer Register is located at offset 41h in the PCI Configuration Space. It is read only. PCI Power Management Capabilities Register (PMC) Offset 42h Note: All bits of this register are loaded from the EEPROM. The register is aliased to BCR36 for testing purposes. Bit Name Description 15-11 PME_SPT PME Support. This 5-bit field indi- cates the power states in which the function may assert PME. A value of 0b for any bit indicates that the function is not capable of asserting the PME signal while in that power state. Bit(11) XXXX1b - PME can be asserted from D0. Bit(12) XXX1Xb - PME can be asserted from D1. Bit(13) XX1XXb - PME can be asserted from D2. Bit(14) X1XXXb - PME can be asserted from D3hot. Bit(15) 1XXXXb - PME can be asserted from D3cold. PME_SPT is read only. |
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