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CS494002 数据表(PDF) 6 Page - Cirrus Logic |
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CS494002 数据表(HTML) 6 Page - Cirrus Logic |
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6 / 100 page ![]() 6 LIST OF TABLES Table 1. PLL Filter Component Values ...............................................................................................37 Table 2. Host Modes for DSPAB ........................................................................................................42 Table 3. Host Modes for DSPC ..........................................................................................................42 Table 4. SPI Communication Signals for DSPAB ...............................................................................43 Table 5. SPI Communication Signals for DSPC .................................................................................46 Table 6. Intel Mode Communication Signals for DSPAB ....................................................................51 Table 6. Parallel Input/Output Registers for DSPAB ..........................................................................52 Table 7. Motorola Mode Communication Signals for DSPAB.............................................................54 Table 8. Parallel Input/Output Registers for DSPC.............................................................................59 Table 9. Intel Mode Communication Signals for DSPC ......................................................................60 Table 10. Motorola Mode Communication Signals for DSPC .............................................................64 Table 11. SRAM Interface Pins ..........................................................................................................70 Table 12. SDRAM Interface Pins ........................................................................................................70 Table 13. SRAM Controller Timing .....................................................................................................71 Table 14. SDRAM Config Register .....................................................................................................71 Table 15. Application Messages from DSPAB ...................................................................................72 Table 16. Boot Write Messages for DSPC .........................................................................................72 Table 17. Boot Read Messages from DSPC ......................................................................................72 Table 18. Digital Audio Input Port .......................................................................................................80 Table 19. Compressed Data Input Port ..............................................................................................80 Table 20. Input Data Type Configuration (Input Parameter A).............................................................................................................81 Table 21. Input Data Format Configuration (Input Parameter B).............................................................................................................81 Table 22. Input SCLK Polarity Configuration (Input Parameter C) ............................................................................................................81 Table 23. Serial Audio Input Port ........................................................................................................82 Table 24. SAI Data Type Configuration (Input Parameter D) ............................................................................................................82 Table 25. Digital Audio Output Port ....................................................................................................82 Table 26. MCLK/SCLK Master Mode Ratios ......................................................................................83 Table 27. Output Clock Configuration (Parameter A)......................................................................................................................84 Table 28. Output Data Configuration Parameter B)...........................................................................84 Table 29. Output SCLK/LRCLK Configuration (Parameter C) .....................................................................................................................84 Table 30. Output SCLK Polarity Configuration (Parameter D) .....................................................................................................................85 Table 31. Example Values to be Sent to DSPAB After Download or Soft Reset................................86 Table 32. Example Values to be Sent to DSPC After Download or Soft Reset ..................................86 |
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