CS494002 datasheet(42/100 Pages) CIRRUS

42 / 100 page

pin name, and pin number of each of these signals

on DSPAB.

6.1.1.1 Writing in SPI for DSPAB

When writing to the device in SPI the same

protocol will be used whether writing a byte, a

message, or even an entire executable download

image. The examples shown in this document can

be expanded to fit any write situation. Figure 30,

"SPI Write Flow Diagram for DSPAB" on page 42

shows a typical write sequence:

The following is a detailed description of an SPI

write sequence with DSPAB.

1) An SPI transfer is initiated when chip select

(FCS) is driven low.

2) This is followed by a 7-bit address and the

read/write bit set low for a write. The address

for DSPAB defaults to 1000000b. It is

necessary to clock this address in prior to any

transfer in order for DSPAB to accept the write.

In other words a byte of 0x80 should be clocked

into the device preceding any write. The 0x80

byte represents the 7-bit address 1000000b,

with the least significant bit set to 0 to designate

a write.

3) The host should then clock data into the device

most significant bit first, one byte at a time. The

data byte is transferred from the shift register to

the DSP input register on the falling edge of the

eighth serial clock. For this reason, the serial

clock should default to low so that eight

transitions from low to high to low will occur

for each byte. A 32

µS byte to byte latency must

be obeyed during run time.

4) When all of the bytes have been transferred,

chip select should be raised to signify an end of

write. Once again it is crucial that the serial

clock transitions from high to low on the last bit

of the last byte before chip select is raised, or a

loss of data will occur.

Thesamewrite routinecould beusedto senda

single byte, a message, or an entire application

code image. From a hardware perspective, it makes

no difference whether communication is by byte or

multiple bytes of any length as long as the correct

hardware protocol is followed.

6.1.1.2 Reading in SPI for DSPAB

A read operation is necessary when DSPAB signals

that it has data to be read. DSPAB does this by

dropping its interrupt request line (FINTREQ) low.

When reading from the device in SPI, the same

protocol will be used whether reading a single byte

or multiple bytes. The examples shown in this

document can be expanded to fit any read situation.

Figure 32, "SPI Read Flow Diagram for DSPAB"

on page 44 shows a typical read sequence:

The following is a detailed description of an SPI

read sequence with DSPAB.

Mnemonic

Pin Name

144-Pin

Package,

Number

100-Pin

Package,

Number

Chip Select

FCS

Serial Clock

FSCCLK

Serial Data In

FSCDIN

Serial Data Out FSCDOUT

Interrupt

Request

FINTREQ

Table 4. SPI Communication Signals for DSPAB

SPI STAR T: FC S (LO W )

W RIT E AD DRESS BYTE

WITH M ODE BIT

SET TO 0 F OR W RITE

MORE DATA?

W R IT ED ATABY TE

SPI STO P: FC S (H IGH )

Figure 30. SPI Write Flow Diagram for DSPAB

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