CS494002 datasheet(64/100 Pages) CIRRUS

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3) The host initiates a write cycle by driving the

CS and DS pins low.

4) The host drives the data byte to the HDAT[7:0]

pins of DSPC.

5) Once the setup time for the write has been met,

the host ends the write cycle by driving the DS

and CS pins high.

6.3.6.2

Writing a 32-bit (4-byte) Word in

Motorola Mode for DSPC

Information provided in this section is intended as

a functional description of how to write control

information to DSPC. The system designer must

ensure that all of the timing constraints of the

Motorola Parallel Host Mode Write Cycle are met.

The flow diagram shown in Figure 43 illustrates

the sequence of events that define a 32-bit (4-byte)

write in Motorola mode. 32-bit (4-byte) writes

should only be done to the Host Message register.

The protocol presented in Figure 43 will now be

described in detail.

1) The host must first drive the A1 and A0 register

address pins of DSPC with the address of the

desired parallel I/O register (A1=A0=0). The

address must be maintained for the duration of

the write cycle, and is latched on the falling

edge of CS.

Host Message:

A[1:0]==00b.

2) The host indicates that this is a write cycle by

driving the R/W pin low.

3) The host initiates a write cycle by driving the

CS and DS pins low.

4) The host drives the most significant data byte

(bits 31:24) to the HDAT[7:0] pins of DSPC.

5) Once the setup time for the data has been met,

the host latches this byte in by driving DS high.

6) The host drive DS low.

7) The host drives the next most significant data

byte, BYTE_B (bits 23:16), to the HDAT[7:0]

R/W (LOW)

ADDRESS A PARALLEL I/O REGISTER

(A[1:0] SET APPROPRIATELY)

CS (HIGH)

CS (LOW)

DS (LOW)

WRITE MS_BYTE TO

HDAT[7:0]

DS (HIGH)

DS (LOW)

WRITEBYTE_BTO

HDAT[7:0]

DS (HIGH)

DS (LOW)

WRITEBYTE_ATO

HDAT[7:0]

DS (HIGH)

DS (LOW)

WRITE LS_BYTE TO

HDAT[7:0]

DS (HIGH)

Figure 47. Motorola Mode, 32-bit (4-byte) Write Flow

Diagram for DSPC

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