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CS494002 数据表(PDF) 22 Page - Cirrus Logic |
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CS494002 数据表(HTML) 22 Page - Cirrus Logic |
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22 / 100 page ![]() 22 1.14 Switching Characteristics — Digital Audio Input (DSPAB) (TA =25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL =20pF) Notes: 1. This timing parameter is defined from the active edge of FSCLKN1/2. The active edge of FSCLKN1/2 is the point at which the data is valid. 2. Slave mode is defined as FSCLKN1/2 and FLRCLKN1/2 driven by an external source. Parameter Symbol Min Max Unit FSCLKN1 period for Slave mode Tsclki 40 - ns FSCLKN1 duty cycle for Slave mode 45 55 % Slave Mode (Note 2) Time from active edge of FSCLKN1(2) to FLRCLKN1(2) transition Tstlr 10 - ns Time from FLRCLKN1(2) transition to FSCLKN1(2) active edge Tlrts 10 - ns FSDATAN1(2) setup to FSCLKN1(2) transition (Note 1) Tsdsus 5- ns FSDATAN1(2) hold time after FSCLKN1(2) transition (Note 1) Tsdhs 5- ns Tsclki Tlrts Tstlr Tsdsus Tsdhs FS C L K N 1 F S DA T A N1 F L RC L K N1 FS C L K N 2 F L RCL K N 2 FS D A TA N 2 Figure 13. Digital Audio Input Data, Slave Clock Timing |
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