CS494002 datasheet(79/100 Pages) CIRRUS

79 / 100 page

pin names, mnemonics and pin numbers associated

with the DAI.

The DAI is fully configurable including support for

I2S and left-justified formats. DAI is programmed

for

slave

clocks,

where

FLRCLKN1

and

FSCLKN1 are inputs. All DAI configuration

messages mustbe sentto DSPAB.

11.3 Compressed Data Input Port

The compressed data input port (CDI) on DSPAB

can be used for both compressed and PCM data

input. Table 19 shows the mnemonic, pin name,

and pin number of the pins associated with the CDI

port on the CS49400.

The CDI port is fully configurable for all data

formats

including:

I2S,

left-justified

and

multichannel formats. FLRCLKN2 and FSCLKN2

on the CDI port are programmed to be inputs. All

CDI configuration messages must be sent to

DSPAB.

11.4 Input Data Hardware Configuration

for CDI and DAI on DSPAB

Both data format (I2S, Left Justified) and data type

(compressed or PCM) are required to fully define

the input port’s hardware configuration. The DAI

and the CDI are configured by the same group of

messages

since

their

configurations

are

interrelated. The naming convention of the input

hardware configuration is as follows:

INPUT AB C

where A, B, C and are the parameters used to fully

define the input port. The parameters are defined as

follows:

A - Data Type

B- Data Format

C - SCLK Polarity

Pin Name

Pin Description

144-Pin

Package,

Number

100-Pin

Package,

Number

FSDATAN1

Serial Data In

131

FSCLKN1

FSTCCLK2

Serial Bit Clock

Secondary STC

Clock

134

FLRCLKN1

Frame Clock

119

Table 18. Digital Audio Input Port

FLRCLKN1

FSCLKN1

FSDATAN1

MSB

LSB

Left

Right

MSB

LSB

Figure 55. I

2SFormat

FLRCLKN1

FSCLKN1

FSDATAN1

MSB

LSB

Left

Right

MSB

LSB

MSB

Figure 56. Left Justified Format (Rising Edge Valid SCLK)

Pin Name

Pin Description

144-Pin

Package,

Number

100-Pin

package,

Number

FSDATAN2

CMPDAT

Serial Data In

Compressed Data

118

FSCLKN2

CMPCLK

Serial Bit Clock

111

FLRCLKN2

CMPREQ

Frame Clock

Data Request Out

117

Table 19. Compressed Data Input Port

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