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CS494002 数据表(PDF) 26 Page - Cirrus Logic

部件名 CS494002
功能描述  Multi-Standard Audio Decoder Family
PDF  100 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS494002 数据表(HTML) 26 Page - Cirrus Logic

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26
1.18 Switching Characteristics — Digital Audio Output
(TA =25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL =20pF)
Notes: 1. DSPC has two Digital Audio Output modules having analogous signal names ending in 0 and 1. Both
DAO ports share a common MCLK but have independent SCLKs and LRCLKs.
2. Master mode timing specifications are characterized, not production tested.
3. Master mode is defined as the CS49400 driving both SCLK0, SCLK1, LRCLK0, and LRCLK1. When
MCLK is an input, it is divided to produce SCLK0, SCLK1, LRCLK0 and LRCLK1.
4. This timing parameter is defined from the non-active edge of SCLK0 and SCLK1. The active edge of
SCLK0 and SCLK1 is the point at which the data is valid.
5. Slave mode is defined as SCLK0, SCLK1, LRCLK0 and LRCLK1 driven by an external source.
Parameter
Symbol
Min
Max
Unit
MCLK period
Tmclk
40
-
ns
MCLK duty cycle
40
60
%
SCLK0, SCLK1 period for Master or Slave mode
(Note 2)
Tsclk
40
-
ns
SCLK0, SCLK1 duty cycle for Master or Slave mode
(Note 2)
45
55
%
Master Mode (Output A1 Mode)
(Note 2, 3)
SCLK0, SCLK1 delay from MCLK rising edge, MCLK as an
input
Tsdmi
15
ns
LRCLK0, LRCLK1 delay from SCLK0, SCLK1 transition,
respectively
(Note 4)
Tlrds
10
ns
AUDATA7–0 delay from SCLK0, SCLK1 transition
(Note 4)
Tadsm
10
ns
Slave Mode (Output A0 Mode)
(Note 5)
Time from active edge of SCLK0, SCLK1 to LRCLK0, LRCLK1
transition
Tstlr
10
-
ns
Time from LRCLK0, LRCLK1 transition to SCLK0, SCLK1
active edge
Tlrts
10
-
ns
AUDATA7–0 delay from SCLK0, SCLK1 transition
(Note 4)
Tadss
15
ns



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