CS494002 datasheet(53/100 Pages) CIRRUS

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before this occurs).

3) Once the data is valid (after waiting the

appropriate time specified in the timing

specifications), the host can read the value of

the selected register from the FDAT[7:0] pins

of DSPAB.

4) The host should now terminate the read cycle

by driving the FCS and FRD pins high.

6.2.6 Motorola Parallel Communication

Mode for DSPAB

The Motorola parallel host communication mode is

implemented using the pins given in Table 7.

Parallel host communication is available only on

the 144-pin package part .

The HOUTRDY bit of the Host Control Register

(A[1:0] = 01b) indicates that the DSP has a

message for the host to read. The FINTREQ pin

can be controlled by the application code, and

allows for another method of requesting that the

host read a message. When the code supports

FINTREQ notification, the FINTREQ pin is

asserted (driven low) whenever the DSP has an

outgoing message for the host.

FINTREQ is useful for informing the host of

unsolicited messages. An unsolicited message is

defined as a message generated by the DSP without

an associated host read request. Unsolicited

messages are used to notify the host of conditions

such as a change in the incoming audio data type

(e.g. PCM --> AC-3). Most unsolicited messages

must be specifically enabled by setting the

appropriate bit in the application’s manager,

enabling autodetection, or enabling other host

notification capabilities.

6.2.6.1 Writing a Byte in Motorola Mode

Information provided in this section is intended as

a functional description of how to write control

information to DSPAB. The system designer must

ensure that all of the timing constraints of the

Motorola Parallel Host Mode Write Cycle are met.

The flow diagram shown in Figure 38 illustrates

the sequence of events that define a one-byte write

in Motorola mode. The protocol presented in

Figure 38 will now be described in detail.

1) The host must drive the FA1 and FA0 register

address pins of DSPAB with the address of the

FCS (HIGH)

FRD (HIGH)

READ BYTE FROM

FDAT[7:0]

FCS (LOW)

FRD (LOW)

ADDRESS A PARALLEL I/O REGISTER

(FA[1:0] SET APPROPRIATELY)

Figure 37. Intel Mode, One-Byte Read Flow Diagram

for DSPAB

Mnemonic

Pin Name

144-Pin

Package,

Number

Chip Select

FCS

Data Strobe

FDS

Read or Write Select

FR/W

FA1

FA0

Interrupt Request

FINTREQ

DATA7

FDAT7

DATA6

FDAT6

DATA5

FDAT5

DATA4

FDAT4

DATA3

FDAT3

DATA2

FDAT2

DATA1

FDAT1

DATA0

FDAT0

Table 7. Motorola Mode Communication Signals for

DSPAB

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