CS494002 datasheet(71/100 Pages) CIRRUS

71 / 100 page

8. BOOT PROCEDURE

In this section the process of booting and

downloading to the CS49400 will be covered as

well as how to perform a soft reset. There are two

ways to boot the DSP:

•

Host Controlled MasterBoot

•

Host Boot Via DSPC

Each of these boot procedures will be described in

detail with pseudocode. The flow charts use the

following messages:

•

Write-C_* Write to DSPC

•

Read-C_* Read from DSPC

•

Write-AB_* Write to DSPAB

•

Read-AB_*Readfrom DSPAB

Note:

When reading from DSPAB the host must

wait for FINTREQ to fall before starting the read

cycle. When reading from DSPC the host must

wait for INTREQ to fall before starting the read

cycle.

Note:

The * can be replaced by SPI, INTEL, or

MOT depending on the mode of host

communication. For each case the general

download algorithm is the same.

Table 16, and Table 17 define the boot write

messages and boot read messages in mnemonic and

actual hex value for DSPAB and DSPC. These

messages will be used in the boot sequence

8.1 Host Controlled Master Boot

A host controlled master boot is a sequence where

a host instructs the DSP to load application code

into itself from external memory. External memory

can either be FLASH or SPI EEPROM.

The

flow

chart given

Figure 52, "Host

Controlled Master Boot (Downloading both a

DSPAB

Application

Code

and

DSPC

Application Code)" on page 72 demonstrates the

interaction required by the microcontroller when

placing the DSP into a host controlled master

mode.

1) A download sequence is started when the host

holds the mode pins appropriately (UHS[2:0]

and FHS[1:0]) and toggles RESET.

2) The

host

must

then

send

the

C_MASTER_SOURCE_MODE boot message

MNEMONIC

VALUE

AB_APP_START

0x03

AB_APP_FAILURE

0xF0

Table 15. Application Messages from DSPAB

MNEMONIC

VALUE

C_RESERVED

0x00 00 00 00

C_SOFT_RESET

0x40 00 00 00

Table 16. Boot Write Messages for DSPC

C_SLAVE_MODE

0x80 00 00 00

C_MASTER_BOOT_FLASH

1110 wwww wrrr rrAA

AAAA AAAA AAAA AAAA

Where

w = SRAM_FLASH_WR_CYCLE

variable found in the SRAM Switch-

ing characteristics table in Section

1.19.

r = SRAM_FLASH_RD_CYCLE

variable found in the SRAM Switch-

ing characteristics table in Section

1.19.

A = 18-bit start address/4

0xEw cb AA AA

MNEMONIC

VALUE

C_BOOT_START

0x00 00 00 01

C_BOOT_SUCCESS

0x00 00 00 02

C_APP_START

0x00 00 00 04

C_BOOT_ERROR_CHECKSUM

0x00 00 00 FF

INVALID_BOOT_TYPE

0x00 00 00 FE

Table 17. Boot Read Messages from DSPC

Table 16. Boot Write Messages for DSPC (Continued)

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