CS494002 datasheet(60/100 Pages) CIRRUS

60 / 100 page

6.3.5.2 Writing a 32-bit (4-byte) Word in Intel

Mode for DSPC

Information provided in this section is intended as

a functional description of how to write control

information to DSPC. The system designer must

ensure that all of the timing constraints of the Intel

Parallel Host Mode Write Cycle are met.

The flow diagram shown in Figure 43 illustrates

the sequence of events that define a 4-byte write in

Intel mode. 32-bit (4-byte) writes should only be

used to write to the Host Message register. The

protocol presented in Figure 43 will now be

described in detail.

1) The host must first drive the A1 and A0 register

address pins of DSPC with the address of the

desired Parallel I/O Register (both low for

A1=A0=0). The address must be maintained

for the duration of the write cycle, and is

latched on the falling edge of CS and WR.

Host Message:

A[1:0]==00b.

2) The host initiates a write cycle by driving the

CS and WR pins low.

3) The host drives the most significant data byte

(bits 31:24) to the HDAT[7:0] pins of DSPC.

4) Once the setup time for the write has been met,

the host drives WR high to strobe in the most

significant data byte.

5) The host drives WR low.

6) The host drives the next most significant data

byte, BYTE_B (bits 23:16), to the HDAT[7:0]

pins of DSPC.

7) Once the setup time for the write has been met,

the host drives WR high to strobe in the data

byte.

8) The host drives WR low.

9) The host drives the next most significant data

byte, BYTE_A (bits 15:8), to the HDAT[7:0]

pins of DSPC.

10) Once the setup time for the write has been met,

the host drives WR high to strobe in the data

byte.

11) The host drives WR low.

12) The host drives the least significant data byte

(bits 7:0) to the HDAT[7:0] pins of DSPC.

13) Once the setup time for the write has been met,

the host drives WR high to strobe in the data

byte.

14) The host drives CS high to end the write

transaction.

6.3.5.3 Reading a Byte in Intel Mode for DSPC

Information provided in this section is intended as

a functional description of how to read control

information from DSPC. The system designer must

ensure that all of the timing constraints of the Intel

Parallel Host Mode Read Cycle are met.

The flow diagram shown in Figure 44 illustrates

the sequence of events that define a one-byte read

in Intel mode. One-byte reads should only be done

with the Host Control register. The protocol

presented in Figure 44 will now be described in

detail.

CS (HIGH)

RD (HIGH)

READ BYTE FROM

HDAT[7:0]

CS (LOW)

RD (LOW)

ADDRESS A PARALLEL I/O REGISTER

(A[1:0] SET APPROPRIATELY)

Figure 44. Intel Mode, One-Byte Read Flow Diagram

for DSPC

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