CS494002 datasheet(18/100 Pages) CIRRUS

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1.12 Switching Characteristics — SPI Control Port Slave Mode (DSPAB)

(TA =25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL =20pF)

Notes: 1. The specification fsck indicates the maximum speed of the hardware. The system designer should be

aware that the actual maximum speed of the communication port may be limited by the DSP application

code. The relevant application code user’s manual should be consulted for the software speed

limitations.

2. Data must be held for sufficient time to bridge the transition time of FSCCLK.

3. FINTREQ goes high only if there is no data to be read from the DSP at the rising edge of FSCCLK for

the second-to-last bit of the last byte of data during a read operation as shown.

4. If FINTREQ goes high as indicated in (Note 3), then FINTREQ is guaranteed to remain high until the

next rising edge of FSCCLK. If there is more data to be read at this time, FINTREQ goes active low

again. Treat this condition as a new read transaction. Raise chip select to end the current read

transaction and then drop it, followed by the 7-bit address and the R/W bit (set to 1 for a read) to start

a new read transaction.

Parameter

Symbol

Min

Max

Units

FSCCLK clock frequency

(Note 1)

fsck

-2

MHz

FCS falling to FSCCLK rising

tcss

FSCCLK low time

tscl

150

FSCCLK high time

tsch

150

Setup time FSCDIN to FSCCLK rising

tcdisu

Hold time FSCCLK rising to FSCDIN

(Note 2)

tcdih

Transition time from FSCCLK to FSCDOUT valid

tscdov

-40

Time from FSCCLK rising to FINTREQ rising

(Note 3)

tscrh

-200

Hold time for FINTREQ from FSCCLK rising

(Note 4, 5)

tscrl

Time from FSCCLK falling to FCS rising

tsccsh

High time between active FCS

tcsht

200

Time from FCS rising to FSCDOUT high-Z

tcscdo

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