CS494002 datasheet(30/100 Pages) CIRRUS

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1.20 Switching Characteristics — SDRAM Interface

(TA =25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL = 20 pF, SD_CLKOUT = SD_CLKIN)

Figure 23. SDRAM Controller Timing Diagram - Load Mode Register Cycle

Parameter

Symbol

Min

Max

Unit

SD_CLKIN high time

tclk_high

0.475*DCLKP

SD_CLKIN low time

tclk_low

0.475*DCLKP

SD_CLKOUT rise/fall time

tclkrf

-1

SD_CLKOUT duty cycle

tclkrf

SD_CLKOUT rising edge to signal valid

-9.8

Signal hold from SD_CLKOUT rising edge

1.0

SD_CLKOUT rising edge to SD_DQMn valid

tDQd

-7.2

SD_DQMn hold from SD_CLKOUT rising edge

tDQh

1.0

SD_DATA valid setup to SD_CLKIN rising edge

tDAs

8.3

SD_DATA valid hold to SD_CLKIN rising edge

tDAh

1.0

SD_CLKOUT rising edge to ADDRn valid

-8.0

SD _CL K O UT

SD _DQ M n

SD_ ADDRn

SD_ DATAn

OP CO DE

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