CS494002 datasheet(36/100 Pages) CIRRUS

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from either an external microcontroller or through

one of the boot procedures listed in Section 8.

3. TYPICAL CONNECTION DIAGRAMS

Four typical connection diagrams have been

presented to illustrate using the part with the

different communication modes available. They

are as follows:

Figure 27, "SPI Control with External Memory -

144 Pin Package" on page 38.

Figure 28, "Intel® Parallel Control Mode - 144 Pin

Package" on page 39.

Figure 29, "Motorola® Parallel Control Mode - 144

Pin Package" on page 40.

The following should be noted when viewing the

typical connection diagrams:

Note:

The pins are grouped functionally in each

of the typical connection diagrams. Please be

aware that the CS49400 symbol may appear

differently in each diagram.

The external memory interface is supported

when a serial or parallel communication mode

has been chosen.

3.1 Multiplexed Pins

The CS49400 incorporates a large amount of

flexibility into a 144 pin package. The pins are

internally multiplexed to serve multiple purposes.

Some pins are designed to operate in one mode at

power up, and serve a different purpose when the

DSP is running. Other pins have functionality

which can be controlled by the application running

on the DSP. In order to better explain the behavior

of the part, the pins which are multiplexed have

been given multiple names. Each name is specific

to the pin’s operation in a particular mode.

In this document, pins will be referred to by their

functionality. Section 12

“Pin Description” on

page 86 describes each pin of the CS49400 and lists

all of its names. Please refer to this section when

exact pin numbers are in question.

3.2 Termination Requirements

The CS49400 incorporates open drain pins which

must be pulled high for proper operation.

FINTREQ and INTREQ are always open drains

which requires a pull-up for proper operation.

Due to the internal, multiplexed design of the pins,

certain signals may or may not require termination

depending on the mode being used. If a parallel

host communication mode is not being used, all

parallel control pins must be terminated or driven

as these pins will come up as high impedance

inputs and will be prone to oscillation if they are

left floating. The specific termination requirements

may vary since the state of some of the GPIO pins

will determine the communication mode at the

rising edge of reset (please see Section 6 “Control”

on page 41 for more information). For the explicit

termination requirements of each communication

mode please see the typical connection diagrams.

Generally a 3.3k Ohm resistor is recommended for

open drain and mode select pins. A 10k Ohm

resistor is sufficient for all other unused inputs.

3.3 Phase Locked Loop Filter

The internal phase locked loop (PLL) of the

CS49400 requires an external filter. The topology

of this filter is shown in the typical connection

diagrams. The component values are shown below.

Care should be taken when laying out the filter

circuitry to minimize trace lengths and to avoid any

high frequency signals. Any noise coupled onto the

filter circuit will be directly coupled into the PLL,

which could affect performance.

Reference Designator

Value

2.2uF

1200pF

68pF

3k Ohm

Table 1. PLL Filter Component Values

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