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CS494002 数据表(PDF) 9 Page - Cirrus Logic |
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CS494002 数据表(HTML) 9 Page - Cirrus Logic |
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9 / 100 page ![]() 9 1.7 Switching Characteristics — CLKIN (TA =25 °C; VDD, PLLVDD = 2.5; VDDSD = 3.3 V; CL =20pF) Parameter Symbol Min Max Unit CLKIN period for internal DSP clock mode Tclki 35 100 ns CLKIN high time for internal DSP clock mode Tclkih 18 ns CLKIN low time for internal DSP clock mode Tclkil 18 ns External Crystal operating frequency Fxtal 10 14 MHz CL KIN Tclkih Tclkil Tclki Figure 2. CLKIN with CLKSEL = VSS = PLL Enable |
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