数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

CS494002 数据表(PDF) 48 Page - Cirrus Logic

部件名 CS494002
功能描述  Multi-Standard Audio Decoder Family
PDF  100 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS494002 数据表(HTML) 48 Page - Cirrus Logic

Back Button CS494002 Datasheet HTML 44Page - Cirrus Logic CS494002 Datasheet HTML 45Page - Cirrus Logic CS494002 Datasheet HTML 46Page - Cirrus Logic CS494002 Datasheet HTML 47Page - Cirrus Logic CS494002 Datasheet HTML 48Page - Cirrus Logic CS494002 Datasheet HTML 49Page - Cirrus Logic CS494002 Datasheet HTML 50Page - Cirrus Logic CS494002 Datasheet HTML 51Page - Cirrus Logic CS494002 Datasheet HTML 52Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 48 / 100 page
background image
48
5) If INTREQ is still low after 4 bytes, another 4
bytes should be clocked out of DSPC.
6) When INTREQ is released, the chip select line
of DSPC should be taken high to end the read
transaction.
All messages read back from DSPC will be in 4-
byte multiples.
6.1.3 FINTREQ Behavior: A Special Case
When communicating with DSPAB there are two
types of messages which force FINTREQ to go
low. These messages are known as solicited
messages and unsolicited messages. For more
information on the specific types of messages that
require a read from the host, one of the application
code user’s guides should be referenced.
In general, when communicating with DSPAB,
FINTREQ will not go low unless the host first
sends a read request command message. In other
words the host must solicit a response from the
DSP. In this environment, the host must read from
DSPAB until FINTREQ goes high again. Once the
FINTREQ pin has gone high it will not be driven
low until the host sends another read request.
When unsolicited messages, such as those used for
Autodetect, have been enabled, the behavior of
FINTREQ is noticeably different. DSPAB will
drop the FINTREQ pin whenever it has an
outgoing message, even though the host may not
have requested data.
There are three ways in which FINTREQ can be
affected by an unsolicited message:
1) During normal operation, while FINTREQ is
high, DSPAB could drop FINTREQ to indicate an
outgoing message, without a prior read request.
2) The host is in the process of reading from
DSPAB, meaning that FINTREQ is already low.
An unsolicited message arrives which forces
FINTREQ to remain low after the solicited
message is read.
3) The host is reading from DSPAB when the
unsolicited message is queued, but FINTREQ goes
high for one period of FSCCLK and then goes low
again before the end of the read cycle.
In case (1) the host should perform a read operation
as discussed in the previous sections.
In case (2) an unsolicited message arrives before
the second to last FSCCLK of the final byte
transfer of a read, forcing the FINTREQ pin to
remain low. In this scenario the host should
continue to read from DSPAB without a stop/start
condition or data will be lost.
In case (3) an unsolicited message arrives between
the second to last FSCCLK and the last FSCCLK
of the final byte transfer of a read. In this scenario,
FINTREQ will transition high for one clock (as if
the read transaction has ended), and then back low
(indicating that more data has queued). This final
case is the most complicated and shall be explained
in detail.
There are two constraints which completely
characterize the behavior of the FINTREQ pin
during a read. The first constraint is that the
FINTREQ pin is guaranteed to remain low until the
second to last FSCCLK (FSCCLK number N-1) of
the final byte being transferred from DSPAB (not
necessarily the second to last bit of the data byte).
The second constraint is that once the FINTREQ
pin has gone high it is guaranteed to remain high
until the rising edge of the last FSCCLK (FSCCLK
number N) of the final byte being transferred from
DSPAB (not necessarily the last bit of the data
byte). If an unsolicited message arrives in the
window of time between the rising edge of the
second to last FSCCLK and the final FSCCLK,
FINTREQ will drop low on the rising edge of the
final FSCCLK as illustrated in the functional
timing diagram shown for the SPI read cycle.
FINTREQ behavior for SPI communication is
illustrated in Figure 31, "SPI Timing for DSPAB"
on page 43. When using SPI communication, the
FINTREQ pin will remain low until the rising edge
of FSCCLK for the data bit D1 (FSCCLK N-1), but
it can go low at the rising edge of FSCCLK for data
bit D0 (FSCCLK N) if an unsolicited message has



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com