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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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CS494002 数据表(PDF) 25 Page - Cirrus Logic |
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CS494002 数据表(HTML) 25 Page - Cirrus Logic |
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25 / 100 page  25 1.17 Switching Characteristics — Parallel Data Input (DSPAB) (TA =25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL =20pF) Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can be defined as follows: Internal Clock Mode: DCLK ~ 60MHz before and during boot, i.e. DCLKP ~ 16.6ns DCLK ~ 86 MHz after boot, i.e. DCLKP ~ 11.6ns It should be noted that DCLK for the internal clock mode is application specific. The application code users guide should be checked to confirm DCLK for the particular application. Parameter Symbol Min Max Unit CMPCLK Period Tcmpclk 4*DCLKP + 10 ns FDAT[7:0] setup before CMPCLK high Tcmpsu 10 ns FDAT[7:0] hold after CMPCLK high Tcmphld 10 ns CMPC LK Tcmpsu Tcmpclk FD AT[7:0] Tcmphld Figure 16. Parallel Data Timing |
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