CS494002 datasheet(65/100 Pages) CIRRUS

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pins of DSPC.

8) Once the setup time for the data has been met,

the host latches this byte in by driving DS high.

9) The host drive DS low.

10) The host drives the next most significant data

byte, BYTE_A (bits 15:8), to the HDAT[7:0]

pins of DSPC.

11) Once the setup time for the data has been met,

the host latches this byte in by driving DS high.

12) The host drive DS low.

13) The host drives the least significant data byte

(bits 7:0) to the HDAT[7:0] pins of DSPC.

14) Once the setup time for the data has been met,

the host latches this byte in by driving DS high.

15) The host ends the write cycle by driving the CS

pin high.

6.3.6.3 Reading a Byte in Motorola Mode for

DSPC

Information provided in this section is intended as

a functional description of how to write control

information to DSPC. The system designer must

ensure that all of the timing constraints of the

Motorola Parallel Host Mode Read Cycle are met.

The flow diagram shown in Figure 48 illustrates

the sequence of events that define a one-byte read

in Motorola mode. Single byte reads should only be

done with the Host Control register. The protocol

presented in Figure 48 will now be described in

detail.

1) The host must first drive the A1 and A0 register

address pins of DSPC with the address of the

desired Parallel I/O Register (A1=0, A0=1).

The address must be maintained for the

duration of the read cycle, and is latched on the

falling edge of CS.

Host Control:

A[1:0]==01b.

2) The host indicates that this is a read cycle by

driving the R/W pin high.

3) The host initiates a read cycle by driving the CS

and DS pins low (bus must be tri-stated by this

time).

4) Once the data is valid (after waiting the

appropriate time specified in the timing

specifications), the host can read the value of

the selected register from the HDAT[7:0] pins

of DSPC.

5) The host should now terminate the read cycle

by driving the CS and DS pins high.

6.3.6.4 Reading a 32-bit (4-byte) word from

DSPC in Motorola mode

Information provided in this section is intended as

a functional description of how to read control

information from DSPC. The system designer must

ensure that all of the timing constraints of the

Motorola Parallel Host Mode Read Cycle are met.

The flow diagram shown in Figure 49, "Motorola

Mode, 32-Bit (4-Byte) Read Flow Diagram for

DSPC" on page 66 illustrates the sequence of

events that define a 32-bit (4-byte) read in

Motorola mode. Reading a 32-bit (4-byte) word

should only be done with the Host Message

CS (HIGH)

DS (HIGH)

RE AD B YTE FROM

HDA T[7 :0]

CS (LOW )

DS (LOW )

R/W (HIGH)

A DDRE SS A PA RALLE L I/O REGISTE R

(A [1:0 ] S ET AP PRO PRIA TE LY)

Figure 48. Motorola Mode, One-Byte Read Flow

Diagram for DSPC

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