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Z8018233FSC 数据表(PDF) 92 Page - Zilog, Inc. |
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Z8018233FSC 数据表(HTML) 92 Page - Zilog, Inc. |
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92 / 109 page  3-92 Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL PRELIMINARY Zilog DS971820600 Z8S180 AC CHARACTERISTICS (Continued) Z8L180 Z8S180 20 MHz 33 MHz No. Sym Parameter Min Max Min Max Unit Note 41 tRFD1 Clock Rise to /RFSH Fall Delay 20 15 ns 42 tRFD2 Clock Rise to /RFSH Rise Delay 20 15 ns 43 tHAD1 Clock Rise to /HALT Fall Delay 15 15 ns 44 tHAD2 Clock Rise to /HALT Rise Delay 15 15 ns 45 tDRQS /DREQi Setup Time to Clock Rise 20 15 ns 46 tDRQH /DREQi Hold Time from Clock Rise 20 15 ns 47 tTED1 Clock Fall to /TENDi Fall Delay 25 15 ns 48 tTED2 Clock Fall to /TENDi Rise Delay 25 15 ns 49 tED1 Clock Rise to E Rise Delay 30 15 ns 50 tED2 Clock Edge to E Fall Delay 30 15 ns 51 PWEH E Pulse Width (High) 25 20 ns 52 PWEL E Pulse Width (Low) 50 40 ns 53 tEr Enable Rise Time 10 10 ns 54 tEf Enable Fall Time 10 10 ns 55 tTOD Clock Fall to Timer Output Delay 75 50 ns 56 tSTDI CSI/O Tx Data Delay Time 75 60 ns (Internal Clock Operation) 57 tSTDE CSI/O Tx Data Delay Time 7.5 tcyc+100 7.5 tcyc+100 ns (External Clock Operation) 58 tSRSI CSI/O Rx Data Setup Time 1 1 tcyc (Internal Clock Operation) 59 tSRHI CSI/O Rx Data Hold Time 1 1 tcyc (Internal Clock Operation) 60 tSRSE CSI/O Rx Data Setup Time 1 1 tcyc (External Clock Operation) 61 tSRHE CSI/O Rx Data Hold Time 1 1 tcyc (External Clock Operation) 62 tRES /RESET Setup time to Clock Fall 40 25 ns 63 tREH /RESET Hold time from Clock Fall 25 15 ns 64 tOSC Oscillator Stabilization Time 20 20 ms 65 tEXr External Clock Rise Time (EXTAL) 10 5 ns 66 tEXf External Clock Fall Time (EXTAL) 10 5 ns 67 tRr /RESET Rise Time 50 50 ms [2] 68 tRf /RESET Fall Time 50 50 ms [2] 69 tIr Input Rise Time (Except EXTAL, /RESET) 50 50 ns [2] 70 tIf Input Fall Time (Except EXTAL, /RESET) 50 50 ns [2] 71 TdCS /MREQ Valid to /ROMCS, /RAMCS Valid Delay 15 10 ns 72 TdIOCS /IORQ Valid to /IOCS Valid Delay 15 10 ns Notes: These AC parameters values are preliminary and subject to change without notice. [1] All specifications reflect 100% output drive (disabled slew rate limiting feature). [2] Specification 1 through 5 refer to PHI clock output. [3] Exceeds characterization (data propagation delay needs to be analyzed). |
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