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数据搜索系统，热门电子元器件搜索 |
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Z8018233FSC 数据表(PDF) 27 Page - Zilog, Inc. |
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Z8018233FSC 数据表(HTML) 27 Page - Zilog, Inc. |
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27 / 109 page  3-27 Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL PRELIMINARY Zilog DS971820600 PROGRAMMING The following subsections explain and define the parameters for I/O Address assignments. The three tables in this section describe the mapping of the common registers shared by the MPU and the 16550 MIMIC. The MPU address refers to the I/O address as accessed from the MPU side (the Z180™ MPU interface side of the 16550 MIMIC). Note that only the lowest eight address lines are decoded for Z182 peripheral access. The full sixteen address lines are decoded for on-chip Z180 MPU access. The PC address (coined because the UART is common in PCs) is the address needed to access the MIMIC registers through the MIMIC interface signals. The MIMIC interface signals are multiplexed with the ESCC channel B and the Port A signals, and must be activated through the System Configuration Register and the Interrupt Edge/Pin MUX Register. Table 7. Z80182/Z8L182 MPU Registers Register Name MPU Addr PC Addr Z80182/Z8L182 MPU Control Registers 0000H to 00x3FH None (Relocatable to 0040H to 007FH or 0080H to 00BFH) PARALLEL PORTS FUNCTIONAL DESCRIPTION The Z80182/Z8L182 has three 8-bit bi-directional Ports. Each bit is individually programmable for input or output (with the exception of PC6 and PC7 which are inputs only). The Ports are controlled through two registers: the Port Direction Control Register and the Port Data Register. (Please see register description for Ports A, B and C). Note: “x” indicates don’t care condition Table 8. Z80182/Z8L182 MIMIC Register MAP Register Name MPU Addr/Access PC Addr/Access MMC MIMIC Master Control Register xxFFH R/W None IUS/IP Interrupt Pending xxFEH R/Wb7 None IE Interrupt Enable xxFDH R/W None IVEC Interrupt Vector xxFCH R/W None TTCR Transmit Time Constant xxFAH R/W None RTCR Receive Time Constant xxFBH R/W None FSCR FIFO Status and Control xxECH R/W7-4 None RTTC Receive Timeout Time Constant xxEAH R/W None TTTC Transmit Timeout Time Constant xxEBH R/W None RBR Receive Buffer Register xxF0H W only 00H DLAB=0 R only THR Transmit Holding Register xxF0H R only 00H DLAB=0 W only IER Interrupt Enable Register xxF1H R only 01H DLAB=0 R/W IIR Interrupt Identification None 02H R only FCR FIFO Control Register xxE9H R only 02H W only MM REGISTER XXE9H W only None LCR Line Control Register xxF3H R only 03H R/W MCR Modem Control Register xxF4H R only 04H R/W LSR Line Status Register xxF5H R/Wb6432 05H R only MSR Modem Status Register xxF6H R/Wb7-4 06H R only SCR Scratch Register xxF7H R only 07H R/W DLL Divisor Latch (LSByte) xxF8H R only 00H DLAB=1 R/W DLM Divisor Latch (MSByte) xxF9H R only 01H DLAB=1 R/W |
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