Z8018233FSC datasheet(73/109 Pages) ZILOG

73 / 109 page

3-73

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

000000

Even Parity Sel.

Stick Parity

Parity Enable

# of Stop Bits

Word Length Sel.

Set Break

DALB

Figure 76. Line Control Register

(PC Read/Write, Address 03H)

(Z180 MPU Read Only, Address xxF3H)

Line Control Register

Bit 7 Divisor Latch Access Bit (DALB)

This bit allow access to the divisor latch by the PC/XT/AT.

If this bit is set to 1, access to the Transmitter, Receiver and

Interrupt Enable Registers is disabled. When an access is

made to address 0 the Divisor Latch Least Significant byte

is accessed. If an access is made to address 1, the Divisor

Latch Most Significant byte is accessed.

Bit 6 - Bit 0

These bits do not affect the Z80182/Z8L182 directly,

however they can be read by the Z180 MPU and the 16550

MIMIC modes can be emulated by the Z180 MPU.

Modem Control Register

Bit 7-5 Reserved

Reserved for future use, always 0.

Bit 4 Loop

When this bit is set to 1, D3-D0 field reflects the status of

Modem Status Register, as follows:

Out 1

DCD

Out 2

DSR

DTR

CTS

RTS

Emulation of the 16550 UART loop back feature must be

done by the Z180 MPU, except in the above conditions.

Bit 3 Out 2

This bit controls the tri-state on the HINTR pin if bits 2 and

1 are 10. Otherwise it can be read by the Z180 MPU.

Bits 2, 1, 0

These bits have no direct control of the 16550 MIMIC

interface and the Z180 MPU must emulate the function if

it is to be implemented.

000000

DDCD

CTS

TERI

DDSR

DCTS

DSR

DCD

Figure 78. Modem Status Register

(PC Read Only, Address 06H)

(Z180 MPU Read/Write bits 7-4, Address xxF6H)

000000

Out 2

Loop

Out 1

RTS

DTR

Reserved

Figure 77. Modem Control Register

(PC Read/Write, Address 04H)

(Z180 MPU Read Only, Address xxF4H)

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Z8018233FSC 数据表(PDF) 73 Page - Zilog, Inc.

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