Z8018233FSC datasheet(60/109 Pages) ZILOG

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Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

/RAMCS AND /ROMCS REGISTERS (Continued)

RAMUBR, RAMLBR RAM Upper Boundary Range,

RAM Lower Boundary Range

These two registers specify the address range for the

/RAMCS signal. When accessed memory addresses are

less than or equal to the value programmed in the RAMUBR

and greater than or equal to the value programmed in the

RAMLBR, /RAMCS is asserted. The A18 signal from the

CPU is taken before it is multiplexed with T

OUT. In the case

that these registers are programmed to overlap,

/ROMCS takes priority over /RAMCS (/ROMCS is asserted

and /RAMCS is inactive).

Chip Select signals are going active for the address range:

/ROMCS: (ROMBR) >= A19-A12 >= 0

/RAMCS: (RAMUBR) >= A19-A12 >= (RAMLBR)

These registers are set to FFH at POR, and the boundary

addresses of ROM and RAM are as follows:

ROM lower boundary address

(fixed) = 00000H

ROM upper boundary address

(ROMBR register) = 0FFFFFH

RAM lower boundary address

(RAMLBR register) = 0FFFFFH

RAM upper boundary address

(RAMUBR register) = 0FFFFFH

Because /ROMCS takes priority over /RAMCS, the latter

will never be asserted until the value in the ROMBR and

RAMLBR registers are re-initialized to lower values.

11111

Upon reset

A19-A12

Figure 57. ROMBR

(Z180 MPU Read/Write, Address xxE8H)

ROMBR ROM Address Boundary Register

This register specifies the address range for the /ROMCS

signal. When accessed, memory addresses are less than

or equal to the value programmed in this register, the

/ROMCS signal is asserted.

The A18 signal from the CPU is obtained before it is

multiplexed with T

OUT. This signal can be forced to a “1”

(inactive state) by setting bit 3 in the System Configuration

ROM area.

Z80182 Improvement to the Wait State Generator

A separate Wait State Generator is provided for access

memory using /ROMCS and /RAMCS. A single 8-bit register

is added to enable/disable this feature as well as provide

two 3-bit fields that provide 1 to 8 waits for each chip select.

WSG Chip Select Register (Z80182 address D8H)

Bit 7

/RAMCS Wait State Generator Enable.

Disable on power-up or reset.

Bits 6-4

/RAMCS Wait States 1 to 8.

Eight wait states on power-up or reset.

Bit 3

/ROMCS Wait State Generator Enable.

Disable on power-up or reset.

Bits 2-0

/ROMCS Wait States 1 to 8.

Eight wait states on power-up or reset.

There are two wait state generators in the Z182. The actual

number of wait states inserted is the greatest number of

both the Z180 WSG and the chip select WSG. In order to

use the Chip Select WSG, the Z180 WSG should be

programmed to 0 wait states.

Figure 58. WSG Chip Select Register

(Z180 MPU Read/Write, Address xxD8H)

D5 D4

/ROMCS

Wait States

1-8

/ROMCS Wait

State Generator

Enable

/RAMCS Wait

States 1-8

/RAMCS Wait State

Generator Enable

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