Z8018233FSC datasheet(55/109 Pages) ZILOG

55 / 109 page

3-55

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

Read Register 3

Ext/Status IP

Tx IP

Rx IP

Rx Character Available

Read Register 0

Zero Count

Tx Buffer Empty

DCD

Sync/Hunt

CTS

Tx Underrun/EOM

Break/Abort

All Sent

Read Register 1

Residue Code 2

Residue Code 1

Residue Code 0

Parity Error

Rx Overrun Error

CRC/Framing Error

End of Frame (SDLC)

D5 D4

D1 D0

BC0

Read Register 6*

BC1

BC2

BC3

BC4

BC5

BC6

BC7

*Can only be accessed if the SDLC FIFO enhancement

is enabled (WR15 bit D2 set to 1)

SDLC FIFO Status and Byte Count (LSB)

Read Register 2

Interrupt

Vector

BC8

Read Register 7*

BC9

BC10

BC11

BC12

BC13

FDA: FIFO Data Available

1 = Status Reads from FIFO

0 = Status Reads from EMSCC

*Can only be accessed if the SDLC FIFO enhancement

is enabled (WR15 bit D2 set to 1)

SDLC FIFO Status and Byte Count (LSB)

FOS: FIFO Overflow Status

1 = FIFO Overflowed

0 = Normal

Figure 52. Write Register Bit Functions (Continued)

Z8018233FSC 数据表(PDF) 55 Page - Zilog, Inc.

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