Z8018233FSC datasheet(65/109 Pages) ZILOG

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DS971820600

Interrupt Enable Register

The IE Register allows each of the 16550/8250 interrupts

to the Z180™ MPU to be masked off individually or globally.

0000000

MIE

Interrupt Enable

6 Enable THR IRQ

5 Enable TTO IRQ

4 RBR IRQ

3 Enable LCR IRQ

2 Enable MCR IRQ

1 Enable DLL/DLM IRQ

0 Enable FCR IRQ

Priority of interrupts are in this order:

(Highest)

THR IRQ

TTO IRQ

RBR IRQ

MCR IRQ

LCR IRQ

DLL IRQ

DLM IRQ

(Lowest)

FCR or Tx OVERRUN IRQ

Interrupt Vector Register

The Interrupt Vector Register contains either the opcode

(Z180 Interrupt Mode 0) or the modified vector used as the

lower address for a Z180 interrupt service routine (Z180

Interrupt Mode 2), depending upon the VIS bit in the MMC

0, then Z180 Mode 0 interrupt is selected; if VIS is 1, then

Z180 Mode 2 is selected. Note that in Z180 Interrupt Mode

0, the data input to the MPU during the interrupt

acknowledge cycle is an instruction opcode; in Z180

Interrupt Mode 2, this data (modified depending on the

source of the interrupt) becomes part of an address from

which to get the starting address of the interrupt service

routine.

000000

0/Opcode

Status/Opcode

Upper Nibble IVEC

Figure 63. IVEC Register

(Z180 MPU, Address xxFCH)

Bits 7-4 Upper Nibble IVEC (Read/Write)

These four bits generate either an opcode for Z180 Interrupt

Mode 0, or the upper four bits of the interrupt modified

vector used as an 8-bit address to support the Z180

Interrupt Mode 2. These bits are read/write and always

read back what was last written to them.

Bits 3-1 Interrupt Modified Vector/Opcode

(Read/Write Table 16)

These three bits are the Interrupt Status bits when VIS in

the MMC register is 1 (Z180 Interrupt Mode 2). If VIS bit is

0, then this field contains bit 3-bit 1 of the opcode. If the VIS

bit is 0, then these bits contain what was last written to

them.

Figure 62. IE Register

(Z180 MPU, Address xxFDH)

Bit 7 Master Interrupt Enable (Read/Write)

If bit 7 is 0, all interrupts from the 16550 MIMIC are masked

off. If this bit is 1, then interrupts are enabled individually by

setting the appropriate bit.

Bit 6 Enable THR Interrupt (Read/Write)

If this bit is 1, it enables the Transmit Holding Register

Interrupt.

Bit 5 Enable TTO Interrupt (Read/Write)

If this bit is 1, it enables the Transmitter Timeout Interrupt.

This interrupts the CPU when characters remain in the

FIFO below the trigger level and the FIFO is not read or

written for the length of time in the transmitter timeout

Bit 4 Enable RBR Interrupt (Read/Write)

If this bit is 1, it enables the Receive Buffer Register

Interrupt.

Bit 3 Enable LCR Interrupt (Read/Write)

If this bit is 1, it enables the Line Control Register interrupt.

Bit 2 Enable MCR Interrupt (Read/Write)

If this bit is 1, it enables the Modem Control Register

Interrupt.

Bit 1 Enable DLL/DLM Interrupt (Read/Write)

If this bit is 1, it enables the Divisor Latch Least and Most

Significant Byte interrupts.

Bit 0 Enable FCR Interrupt (Read/Write)

If this bit is 1 , then interrupts are enabled for a PC write to

the FIFO control register (FCR) or for occurrence of Tx

Overrun.

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