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Z8018233FSC 数据表(PDF) 2 Page - Zilog, Inc. |
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Z8018233FSC 数据表(HTML) 2 Page - Zilog, Inc. |
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2 / 109 page ![]() 3-2 Z80182/Z8L182 ZILOG INTELLIGENT PERIPHERAL PRELIMINARY Zilog DS971820600 GENERAL DESCRIPTION (Continued) Z8S180 (Static Z80180) MPU Core Address Decode 8-Bit Parallel Port C 8-Bit Parallel Port B 8-Bit Parallel Port A 85230 ESCC Channel B MUX MUX 16550 MIMIC Interface EV1 EV2 D7-D0 Control A19-A0 Tx Data Rx Data ESCC Control /ROMCS /RAMCS GLU Logic 85230 ESCC Channel A Bus Transceiver MUX /TRxCB 16550 MIMIC or ESCC 85230 Ch. B and Port A 85230 ESCC Ch. A or Port C Z180 Signals or Port B Note: Conventional use of the term "MPU side" refers to all interface through the Z180 MPU core and "PC side" refers to all interface through the16550 MIMIC interface. Figure 1. Z80182/Z8L182 Functional Block Diagram |
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