Z8018233FSC datasheet(67/109 Pages) ZILOG

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3-67

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

Bit 0 16450 MIMIC Mode Enable

(Reset value=0) This bit = 1 will force the mimic into 16450

mode. Bit 0 in the FCR reg is forced to zero as well as the

mimic internal FIFO enable. When used, this bit should be

programmed at MIMIC initialization and not modified

afterwards.

111111

Rec Timeout Constant

Figure 65. Receive Timeout Timer Constant

(Z180 MPU Read/Write, Address xxEAH)

This register contains an 8-bit constant for emulation of the

16550 four character timeout feature. Software must

determine the value to load into this register based on the

bit rate and word length specified by the MIMIC interface

with the PC. This timer receives its input from the /TRxCB

Clock of the ESCC. This timer is enabled to down count

when the enable bit in the FSR register is set and the trigger

level interrupt has not been activated on the RCVR FIFO.

The counter reloads and counts down each time there is

a read or write to the RCVR FIFO.

The receive timeout timer is enhanced to emulate the

actual 16550 when bit 1 of the FIFO status and control

should be programmed for four character timers (40d,

8-N-1).

11111

Transmitter Time Constant

Figure 66. Transmit Timeout Timer Constant

(Z180 MPU Read/Write, Address xxEBH)

This register contains an 8-bit constant for determining the

interval for the Transmit Timeout Timer. If allowed to

decrement to zero, this timer interrupts the MPU by setting

the THR bit in the IUS/IP register. This timer receives its

input from the /TRxCB Clock of the SCC. The timer is

enabled to down count when the enable bit in the FSR

on the XMIT FIFO. The counter reloads each time there is

a read or write to the XMIT FIFO.

Transmit And Receive Timers

Because of the speed at which data transfers can take

place between the Z180™ MPU and the PC/XT/AT, two

timers have been added to alleviate any software problems

that a high speed parallel data transfer might cause. These

timers allow the programmer to slow down the data transfer

just as if the 16550 MIMIC interface had to shift the data in

and out serially. The Timers receive their input from the

/TRxCB Clock since, in 16550 MIMIC mode, the ESCC

channel B is disabled. For example, the clock source for

the 8-bit registers: RTTC (Receive Timeout Time Constant,

xxEAH), TTTC (Transmit Timeout Time Constant, xxEBH),

TTCR (Transmit Time Constant Register, xxFAH) and

RTCR (Receive Time Constant Register, xxFBH) uses the

/TRxCB Clock output. The /TRxCB Clock output needs to

be generated by the ESCC’s channel B's 16-bit BRG as its

clock source, thus allowing the programmer to access a

total of 24 bits as a timer to slow down the data transfer.

In most cases, ESCC Ch. B BRG should be programmed

to output at a frequency equivalent to the desired serial

transfer rate. The output of the BRG should be routed to the

/TRxCB pin.

11111

XMIT Timeout Constant

Figure 67. Transmitter Time Constant Register

(Z180 MPU Read/Write, Address xxFAH)

Z8018233FSC 数据表(PDF) 67 Page - Zilog, Inc.

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