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Z8018233FSC 数据表(PDF) 32 Page - Zilog, Inc.

部件名 Z8018233FSC
功能描述  ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP??
PDF  109 Pages
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制造商  ZILOG [Zilog, Inc.]
网页  http://www.zilog.com
标志 ZILOG - Zilog, Inc.

Z8018233FSC 数据表(HTML) 32 Page - Zilog, Inc.

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Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
PRELIMINARY
Zilog
DS971820600
ASCI CHANNELS CONTROL REGISTERS (Continued)
MPBT
MP
/CTS/
PS
SS2
SS1
SS0
Invalid
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
R/W
CNTLB1
Clock Source and Speed Select
Addr 03H
Bit
Upon Reset
DR
PE0
Divide Ratio
Parity Even or Odd
Read - Status of /CTS pin
Write - Select PS
Multiprocessor
Multiprocessor Bit Transmit
General
PS = 0
PS = 1
Divide Ratio
(Divide Ratio = 10)
(Divide Ratio = 30)
SS, 2, 1, 0
DR = 0 (x16)
DR = 1 (x64)
DR = 0 (x16)
DR = 1 (x64)
000
Ø
÷ 160
Ø
÷ 640
Ø
÷ 480
Ø
÷ 1920
001
Ø
÷ 320
Ø
÷ 1280
Ø
÷ 960
Ø
÷ 3840
010
Ø
÷ 640
Ø
÷ 2580
Ø
÷ 1920
Ø
÷ 7680
011
Ø
÷ 1280
Ø
÷ 5120
Ø
÷ 3840
Ø
÷ 15360
100
Ø
÷ 2560
Ø
÷ 10240
Ø
÷ 7680
Ø
÷ 30720
101
Ø
÷ 5120
Ø
÷ 20480
Ø
÷ 15360
Ø
÷ 61440
110
Ø
÷ 10240
Ø
÷ 40960
Ø
÷ 30720
Ø
÷ 122880
*111
External Clock (Frequency < Ø
÷ 40)
Note:
* Baud rate is external clock rate
÷ 16; therefore, Ø ÷ (40 x 16)
is maximum baud rate using external clocking.
Figure 12. ASCI Control Register B (Ch. 1)



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